R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Configuration Switching Characteristics
V
CC
RE-PROGRAM
>300 ns
T
POR
PROGRAM
INIT
T
PI
T
T
CCLK
ICCK
CCLK Output or Input
<300 ns
Mode Pins
(Required)
DONE Response
I/O
<300 ns
DS060_33_080400
Master Mode
Symbol
Description
Min
40
Max
130
200
Units
T
Power-on reset
ms
POR
T
Program Latency
30
µs per CLB column
PI
T
CCLK (output) delay
40
250
µs
ns
ns
ICCK
CCLK
CCLK
T
T
CCLK (output) period, slow
CCLK (output) period, fast
640
100
2000
250
Slave Mode
Symbol
Description
Power-on reset
Min
10
30
4
Max
33
200
-
Units
T
ms
POR
T
Program latency
µs per CLB column
PI
T
CCLK (input) delay (required)
CCLK (input) period (required)
µs
ICCK
T
80
-
ns
CCLK
DS060 (v1.6) September 19, 2001
Product Specification
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1-800-255-7778
41
XILINX [ XILINX, INC ]
