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XCS20-3PQ208C 参数 Datasheet PDF下载

XCS20-3PQ208C图片预览
型号: XCS20-3PQ208C
PDF下载: 下载PDF文件 查看货源
内容描述: 斯巴达和Spartan-XL系列现场可编程门阵列 [Spartan and Spartan-XL Families Field Programmable Gate Arrays]
分类和应用: 现场可编程门阵列
文件页数/大小: 82 页 / 848 K
品牌: XILINX [ XILINX, INC ]
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R
Spartan and Spartan-XL Families Field Programmable Gate Arrays  
Spartan Pin-to-Pin Output Parameter Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Pin-to-pin timing parameters are  
derived from measuring external and internal test patterns  
and are guaranteed over worst-case operating conditions  
(supply voltage and junction temperature). Listed below are  
representative values for typical pin locations and normal  
clock loading. For more specific, more precise, and  
worst-case guaranteed data, reflecting the actual routing  
structure, use the values provided by the static timing ana-  
lyzer (TRCE in the Xilinx Development System) and  
back-annotated to the simulation netlist. These path delays,  
provided as a guideline, have been extracted from the static  
timing analyzer report.  
Spartan Output Flip-Flop, Clock-to-Out  
Speed Grade  
-4  
-3  
Symbol  
Description  
Device  
Max  
Max  
Units  
Global Primary Clock to TTL Output using OFF  
T
Fast  
XCS05  
XCS10  
XCS20  
XCS30  
XCS40  
XCS05  
XCS10  
XCS20  
XCS30  
XCS40  
5.3  
5.7  
8.7  
9.1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ICKOF  
6.1  
9.3  
6.5  
9.4  
6.8  
10.2  
11.5  
12.0  
12.2  
12.8  
12.8  
T
Slew-rate limited  
9.0  
ICKO  
9.4  
9.8  
10.2  
10.5  
Global Secondary Clock to TTL Output using OFF  
T
Fast  
XCS05  
XCS10  
XCS20  
XCS30  
XCS40  
XCS05  
XCS10  
XCS20  
XCS30  
XCS40  
5.8  
6.2  
9.2  
9.6  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ICKSOF  
6.6  
9.8  
7.0  
9.9  
7.3  
10.7  
12.0  
12.5  
12.7  
13.2  
14.3  
T
Slew-rate limited  
9.5  
ICKSO  
9.9  
10.3  
10.7  
11.0  
Delay Adder for CMOS Outputs Option  
T
Fast  
All devices  
All devices  
0.8  
1.5  
1.0  
2.0  
ns  
ns  
CMOSOF  
T
Slew-rate limited  
CMOSO  
Notes:  
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and  
where all accessible IOB and CLB flip-flops are clocked by the global clock net.  
2. Output timing is measured at ~50% V threshold with 50 pF external capacitive load. For different loads, see Figure 33.  
CC  
3. OFF = Output Flip-Flop  
DS060 (v1.6) September 19, 2001  
www.xilinx.com  
47  
Product Specification  
1-800-255-7778  
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