R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Length Count Match
CCLK Period
CCLK
F
DONE
C1
C2
C2
C3
C3
C4
C4
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
I/O
CCLK_NOSYNC
GSR Active
Heavy lines describe
default timing
C2
C3
C4
DONE IN
F
DONE
I/O
C1, C2 or C3
CCLK_SYNC
Di
Di+1
Di+1
GSR Active
Di
F
DONE
I/O
C1
U2
U2
U3
U3
U4
UCLK_NOSYNC
U4
GSR Active
U2
U3
U4
DONE IN
F
DONE
I/O
C1
U2
UCLK_SYNC
Di
Di+1
Di+2
Di+2
GSR Active
Di Di+1
Synchronization
Uncertainty
UCLK Period
DS060_39_082801
Figure 31: Start-up Timing
•
•
Wait for INIT to go High.
Configuration Through the Boundary Scan
Pins
Sequence the boundary scan Test Access Port to the
SHIFT-DR state.
Spartan/XL devices can be configured through the bound-
ary scan pins. The basic procedure is as follows:
•
Toggle TCK to clock data into TDI pin.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
•
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
For more detailed information, refer to the Xilinx application
note, "Boundary Scan in FPGA Devices." This application
note applies to Spartan and Spartan-XL devices.
•
Issue the CONFIG command to the TMS input.
DS060 (v1.6) September 19, 2001
Product Specification
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