R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Configuration
The 0010 preamble code indicates that the following 24 bits
represent the length count for serial modes. The length
count is the total number of configuration clocks needed to
load the complete configuration data. (Four additional con-
figuration clocks are required to complete the configuration
process, as discussed below.) After the preamble and the
length count have been passed through to any device in the
daisy chain, its DOUT is held High to prevent frame start
bits from reaching any daisy-chained devices. In Spar-
tan-XL Express mode, the length count bits are ignored,
and DOUT is held Low, to disable the next device in the
pseudo daisy chain.
V
No
CC
Valid
Boundary Scan
Instructions
Available:
Yes
Test MODE, Generate
One Time-Out Pulse
of 16 or 64 ms
PROGRAM
= Low
Yes
Keep Clearing
Configuration
Memory
EXTEST*
SAMPLE/PRELOAD
BYPASS
CONFIGURE*
(* if PROGRAM = High)
Completely Clear
Configuration Memory
Once More
~1.3 µs per Frame
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configura-
tion clock is selected by the bitstream, the slower clock rate
is used until this configuration bit is detected.
INIT
No
High? if
Master
Master Delays Before
Sampling Mode Line
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error by
pulling the open-drain INIT pin Low. After all configuration
frames have been loaded into an FPGA using a serial
mode, DOUT again follows the input data so that the
remaining data is passed on to the next device. In
Spartan-XL Express mode, when the first device is fully pro-
grammed, DOUT goes High to enable the next device in the
chain.
Yes
Sample
Mode Line
Master CCLK
Goes Active
Load One
Configuration
Data Frame
Yes
Frame
Error
Pull INIT Low
and Stop
Delaying Configuration After Power-Up
No
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 30.)
SAMPLE/PRELOAD
Config-
uration
memory
Full
No
BYPASS
Yes
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the FPGA keeps clearing its configuration memory.
When PROGRAM goes High, the configuration memory is
cleared one more time, followed by the beginning of config-
uration, provided the INIT input is not externally held Low.
Note that a Low on the PROGRAM input automatically
forces a Low on the INIT output. The Spartan/XL PRO-
GRAM pin has a permanent weak pull-up. Avoid holding
PROGRAM Low for more than 500 µs.
Pass
Configuration
Data to DOUT
CCLK
Count Equals
Length
No
Count
Yes
Start-Up
Sequence
F
Operational
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the FPGA
to wait after completing the configuration memory clear
operation. When INIT is no longer held Low externally, the
device determines its configuration mode by capturing the
state of the Mode pins, and is ready to start the configura-
EXTEST
SAMPLE PRELOAD
BYPASS
If Boundary Scan
is Selected
USER 1
USER 2
CONFIGURE
READBACK
DS060_30_080400
tion process. A master device waits up to an additional
300 µs to make sure that any slaves in the optional daisy
chain have seen that INIT is High.
Figure 30: Power-up Configuration Sequence
DS060 (v1.6) September 19, 2001
Product Specification
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35
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