R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
For more details on Configuration, refer to the Xilinx Appli-
cation Note "FPGA Configuration Guidelines" (XAPP090).
options in the bitstream generation software. Heavy lines in
Figure 31 show the default timing. The thin lines indicate all
other possible timing options. The start-up logic must be
clocked until the "F" (Finished) state is reached.
Start-Up
Start-up is the transition from the configuration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial configuration data where
most outputs are 3-stated, to normal operation with I/O pins
active in the user system. Start-up must make sure that the
user logic ‘wakes up’ gracefully, that the outputs become
active without causing contention with the configuration sig-
nals, and that the internal flip-flops are released from the
Global Set/Reset (GSR) at the right time.
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data source
and avoiding any contention when the I/Os become active
one clock later. GSR is then released another clock period
later to make sure that user operation starts from stable
internal conditions. This is the most common sequence,
shown with heavy lines in Figure 31, but the designer can
modify it to meet particular requirements.
Start-Up Clock
Normally, the start-up sequence is controlled by the internal
device oscillator (CCLK), which is asynchronous to the sys-
tem clock. As a configuration option, they can be triggered
by an on-chip user net called UCLK. This user net can be
accessed by placing the STARTUP library symbol, and the
start-up modes are known as UCLK_NOSYNC or
UCLK_SYNC. This allows the device to wake up in synchro-
nism with the user system.
Start-Up Initiation
Two conditions have to be met in order for the start-up
sequence to begin:
•
•
The chip's internal memory must be full, and
The configuration length count must be met, exactly.
In all configuration modes except Express mode, Spar-
tan/XL devices read the expected length count from the bit-
stream and store it in an internal register. The length count
varies according to the number of devices and the composi-
tion of the daisy chain. Each device also counts the number
of CCLKs during configuration.
DONE Pin
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by the bitstream generation software.
In Express mode, there is no length count. The start-up
sequence for each device begins when the device has
received its quota of configuration data. Wiring the DONE
pins of several devices together delays start-up of all
devices until all are fully configured.
The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then be
used as input to the start-up control logic. This is called
“Start-up Timing Synchronous to Done In” and is selected
by either CCLK_SYNC or UCLK_SYNC. When DONE is not
used as an input, the operation is called “Start-up Timing
Not Synchronous to DONE In,” and is selected by either
CCLK_NOSYNC or UCLK_NOSYNC. Express mode con-
figuration always uses either CCLK_SYNC or UCLK_SYNC
timing, while the other configuration modes can use any of
the four timing sequences.
Start-Up Events
The device can be programmed to control three start-up
events.
•
•
The release of the open-drain DONE output
The termination of the Global Three-State and the
change of configuration-related pins to the user
function, activating all IOBs.
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a com-
mon user clock, or to guarantee that all devices are suc-
cessfully configured before any I/Os go active.
•
The termination of the Global Set/Reset initialization of
all CLB and IOB storage elements.
Figure 31 describes start-up timing in detail. The three
events — DONE going High, the internal GSR being
de-activated, and the user I/O going active — can all occur
in any arbitrary sequence. This relative timing is selected by
36
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DS060 (v1.6) September 19, 2001
Product Specification
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