R
Platform Flash In-System Programmable Configuration PROMS
V
CCO
External
(5)
Oscillator
4.7 kΩ
(2)
4.7 kΩ
(1)
V
CCJ
V
CCO
V
CCINT
V
CCINT
V
CCO
V
CCJ
(2)
(2)
D[0:7]
D[0:7]
MODE PINS
(1)
I/O
I/O
1KΩ
1KΩ
(3)
(3)
RDWR_B
CS_B
XCFxxP
Platform Flash
PROM
CLK
(5)
Xilinx FPGA
Slave SelectMAP
CCLK
DONE
CE
CEO
OE/RESET
TDI
TMS
TCK
TDO
TDO
GND
TDI
TMS
TCK
CF
BUSY
(6)
(4)
D[0:7]
INIT_B
PROG_B
BUSY
(4)
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
TDO
(4)
...OPTIONAL
Slave FPGAs
with
identical
configurations
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down externally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-
frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or, optionally, the
CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal
is used, then CLKOUT must be tied to a 4.7 KΩ resistor pulled up to V
CCO
.
6 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be
tied to V
CCO
via a 4.7 kΩ pull-up resistor.
ds123_15_122105
Figure 10:
Configuring in Slave SelectMAP Mode
DS123 (v2.9) May 09, 2006
18
XILINX [ XILINX, INC ]
