R
Platform Flash In-System Programmable Configuration PROMS
V
CCJ
V
CCO
V
CCINT
V
CCJ
V
CCO
V
CCINT
V
CCO
(2)
External
(5)
Oscillator
4.7 kΩ
4.7 kΩ
(1)
V
CCINT
V
CCO
V
CCJ
(2)
(2)
D[0:7]
VCCINT
V
CCO
V
CCJ
(2)
(2)
D[0:7]
D[0:7]
MODE PINS
(1)
D[0:7]
I/O
(3)
1KΩ
MODE PINS
(1)
RDWR_B
CS_B
RDWR_B
CS_B
I/O
(3)
1KΩ
ds123_18_122105
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
TDI
TMS
TCK
TDO
TDI
TMS
TCK
CLK
(5)
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
CLK
(5)
CE
CEO
Xilinx FPGA
Slave SelectMAP
CCLK
DONE
INIT_B
PROG_B
BUSY
(4)
Xilinx FPGA
Slave SelectMAP
CCLK
DONE
INIT_B
PROG_B
BUSY
(4)
CE
CEO
CF
(6)
(4)
OE/RESET
BUSY
OE/RESET
CF
TDI
TMS
TCK
TDO
(6)
(4)
BUSY
TDO
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
EN_EXT_SEL
REV_SEL[1:0]
GND
EN_EXT_SEL
REV_SEL[1:0]
GND
GND
GND
EN_EXT_SEL
Design
Revision
Control
Logic
REV_SEL[1:0]
CF
DONE
PROG_B
CS_B[1:0]
Notes:
1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2. For compatible voltages, refer to the appropriate data sheet.
3. RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4. The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high
frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5. In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or optionally the
CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is
used, then it must be tied to a 4.7KΩ resistor pulled up to V
CCO
.
6 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be
tied to V
CCO
via a 4.7 kΩ pull-up resistor
Figure 13:
Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode
DS123 (v2.9) May 09, 2006
21
XILINX [ XILINX, INC ]
