R
Platform Flash In-System Programmable Configuration PROMS
V
CCO
External
(3)
Oscillator
4.7 kΩ
(2)
4.7 kΩ
(1)
V
CCJ
V
CCO
V
CCINT
V
CCINT
(2)
V
CCO
(2)
V
CCJ
D0
DIN
MODE PINS
(1)
DIN
CCLK
Platform Flash
PROM
CLK
(3)
Xilinx FPGA
Slave Serial
CCLK
DONE
DOUT
INIT_B
PROG_B
DONE
INIT_B
PROG_B
...OPTIONAL
Slave FPGAs
with
identical
configurations
CE
CEO
OE/RESET
TDI
TMS
TCK
TDO
TDO
GND
TDI
TMS
TCK
CF
(4)
DIN
CCLK
DONE
INIT_B
PROG_B
...OPTIONAL
Daisy-chained
Slave FPGAs
with
different
configurations
TDI
TMS
TCK
TDO
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or
optionally—for the XCFxxP Platform Flash PROM only—the CLKOUT signal can be used to drive the
FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then CLKOUT must
be tied to a 4.7KΩ resistor pulled up to V
CCO
.
4 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.
For the
XCFxxP, if CF is not connected to PROGB, then it must be tied to V
CCO
via a 4.7 kΩ pull-up resistor.
ds123_12_122105
Figure 7:
Configuring in Slave Serial Mode
DS123 (v2.9) May 09, 2006
15
XILINX [ XILINX, INC ]
