R
Platform Flash In-System Programmable Configuration PROMS
V
CCJ
V
CCO
V
CCINT
V
CCJ
V
CCO
V
CCINT
V
CCO
(2)
External
(3)
Oscillator
(1)
4.7 kΩ
4.7 kΩ
V
CCINT
V
CCO(2)
V
CCJ
(2)
D0
V
CCINT
V
CCO
V
CCJ
(2)
(2)
D0
DIN
MODE PINS
(1)
DOUT
DIN
MODE PINS
(1)
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
CLK
(3)
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
CLK
(3)
Xilinx FPGA
Slave Serial
CCLK
DONE
INIT_B
PROG_B
Xilinx FPGA
Slave Serial
CCLK
DONE
INIT_B
PROG_B
CE
CEO
CF
(4)
CE
CEO
CF
(4)
OE/RESET
OE/RESET
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDI
TMS
TCK
TDO
EN_EXT_SEL
REV_SEL[1:0]
GND
EN_EXT_SEL
REV_SEL[1:0]
GND
GND
GND
EN_EXT_SEL
Design
Revision
Control
Logic
REV_SEL[1:0]
DONE
CF / PROG_B
Notes
1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2. For compatible voltages, refer to the appropriate data sheet.
3. In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally the CLKOUT
signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used,
then CLKOUT must be tied to a 4.7 KΩ resistor pulled up to V
CCO
.
4. For the XCFxxP the CF pin is a bidirectional pin.
For the XCFxxP, if CF is not connected to PROGB, then it
must be tied to V
CCO
via a 4.7 kΩ pull-up resistor.
ds123_17_122105
Figure 12:
Configuring Multiple Devices with Design Revisioning in Slave Serial Mode
DS123 (v2.9) May 09, 2006
20
XILINX [ XILINX, INC ]
