R
Platform Flash In-System Programmable Configuration PROMS
V
CCO(2)
4.7 kΩ
4.7 kΩ
(1)
V
CCJ
V
CCO
V
CCINT
V
CCINT
V
CCO(2)
V
CCJ
(2)
D[0:7]
D[0:7]
MODE PINS
(1)
I/O
(3)
I/O
1KΩ
1KΩ
(3)
RDWR_B
CS_B
XCFxxP
Platform Flash
PROM
CLK
CE
CEO
OE/RESET
TDI
TMS
TCK
TDO
TDO
GND
TDI
TMS
TCK
CF
BUSY
(5)
(4)
Xilinx FPGA
Master SelectMAP
CCLK
DONE
D[0:7]
INIT_B
PROG_B
BUSY
(4)
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
TDO
(4)
...OPTIONAL
Slave FPGAs
with
identical
configurations
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-
frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be
tied to V
CCO
via a 4.7 kΩ pull-up resistor.
ds123_14_122105
Figure 9:
Configuring in Master SelectMAP Mode
DS123 (v2.9) May 09, 2006
17
XILINX [ XILINX, INC ]
