R
Platform Flash In-System Programmable Configuration PROMS
Configuration PROM to FPGA Device Interface Connection Diagrams
V
CCO
(2)
4.7 kΩ
4.7 kΩ
(1)
V
CCJ
V
CCO
V
CCINT
V
CCINT
V
CCO(2)
(2)
V
CCJ
D0
DIN
MODE PINS
(1)
DIN
CCLK
Platform Flash
PROM
CLK
CE
CEO
OE/RESET
TDI
TMS
TCK
TDO
TDO
GND
TDI
TDI
TMS
TCK
CF
(3)
Xilinx FPGA
Master Serial
CCLK
DONE
DOUT
INIT_B
PROG_B
DONE
INIT_B
PROG_B
...OPTIONAL
Slave FPGAs
with
identical
configurations
DIN
CCLK
DONE
INIT_B
PROG_B
...OPTIONAL
Daisy-chained
Slave FPGAs
with
different
configurations
TMS
TCK
TDO
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin. For the
XCFxxP, if CF is not connected to PROGB, then it must be tied to V
CCO
via a 4.7 kΩ pull-up resistor.
ds123_11_122105
Figure 6:
Configuring in Master Serial Mode
DS123 (v2.9) May 09, 2006
14
XILINX [ XILINX, INC ]
