Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 62: Regional Clock Switching Characteristics (BUFR) (Cont’d)
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
TBRDO_O
Propagation delay from CLR to O
0.69
0.74
0.80
1.12
ns
Maximum Frequency
(1)
FMAX
Regional clock tree (BUFR)
500
420
300
300
MHz
Notes:
1. The maximum input frequency to the BUFR is the BUFIO F
frequency.
MAX
Table 63: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol Description
BUFH delay from I to O
Speed Grade
Units
-3
-2
-1
-1L
TBHCKO_O
BHCCK_CE/TBHCKC_CE
0.10
0.11
0.13
0.15
ns
ns
0.04/
0.04
0.04/
0.04
0.05/
0.05
0.04/
0.04
T
CE pin Setup and Hold
Maximum Frequency
FMAX
Horizontal clock buffer (BUFH)
800
750
700
667
MHz
MMCM Switching Characteristics
Table 64: MMCM Specification
Speed Grade
Symbol
Description
Units
-3
800
10
-2
750
10
-1
700
10
-1L
700
10
FINMAX
FINMIN
FINJITTER
Maximum Input Clock Frequency(1)
Minimum Input Clock Frequency
MHz
MHz
Maximum Input Clock Period Jitter
< 20% of clock input period or 1 ns Max
(2)
FINDUTY
Allowable Input Duty Cycle: 10—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Dynamic Phase Shift Clock Frequency
Maximum Dynamic Phase Shift Clock Frequency
Minimum MMCM VCO Frequency
25/75
30/70
35/65
40/60
45/55
%
%
%
%
%
FMIN_PSCLK
FMAX_PSCLK
FVCOMIN
0.01
550
0.01
500
0.01
450
0.01
450
MHz
MHz
MHz
MHz
MHz
MHz
ns
600
600
600
600
FVCOMAX
Maximum MMCM VCO Frequency
1600
1.00
4.00
0.12
1440
1.00
4.00
0.12
1200
1.00
4.00
0.12
Note 3
0.20
100
1200
1.00
4.00
0.12
FBANDWIDTH
Low MMCM Bandwidth at Typical(3)
High MMCM Bandwidth at Typical(3)
Static Phase Offset of the MMCM Outputs(4)
MMCM Output Jitter(5)
TSTATPHAOFFSET
TOUTJITTER
TOUTDUTY
TLOCKMAX
FOUTMAX
MMCM Output Clock Duty Cycle Precision(6)
MMCM Maximum Lock Time
0.15
100
800
4.69
0.20
100
750
4.69
0.20
100
700
4.69
ns
µs
MMCM Maximum Output Frequency
MMCM Minimum Output Frequency(7)(8)
External Clock Feedback Variation
700
MHz
MHz
FOUTMIN
4.69
TEXTFDVAR
< 20% of clock input period or 1 ns Max
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
52
XILINX [ XILINX, INC ]
