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XC6VSX475T-1FFG1156I 参数 Datasheet PDF下载

XC6VSX475T-1FFG1156I图片预览
型号: XC6VSX475T-1FFG1156I
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 1098MHz, 476160-Cell, CMOS, PBGA1156, 35 X 35 MM, LEAD FREE, FBGA-1156]
分类和应用: 时钟可编程逻辑
文件页数/大小: 65 页 / 1429 K
品牌: XILINX [ XILINX, INC ]
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics  
Speed Grade  
Table 58: DSP48E1 Switching Characteristics (Cont’d)  
Symbol  
Description  
Units  
-1  
(XC)  
-1  
(XQ)  
-3  
-2  
-1L  
TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_  
{PCOUT, CARRYCASCOUT, MULTSIGNOUT}  
{PCIN, CARRYCASCIN,  
MULTSIGNIN} input to {PCOUT,  
CARRYCASCOUT,  
1.28 1.46  
1.72  
1.72  
2.06  
ns  
MULTSIGNOUT} output  
Clock to Outs from Output Register Clock to Output Pins  
TDSPCKO_{P, CARRYOUT}_PREG  
CLK (PREG) to {P, CARRYOUT} 0.38 0.43  
output  
0.50  
0.66  
0.50  
0.66  
0.57  
0.76  
ns  
ns  
TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_PREG CLK (PREG) to  
{CARRYCASCOUT, PCOUT,  
MULTSIGNOUT} output  
0.50 0.56  
Clock to Outs from Pipeline Register Clock to Output Pins  
TDSPCKO_{P, CARRYOUT}_MREG  
CLK (MREG) to {P, CARRYOUT} 1.72 1.96  
output  
2.30  
2.43  
2.30  
2.43  
2.69  
2.88  
ns  
ns  
TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MREG CLK (MREG) to {PCOUT,  
1.81 2.06  
CARRYCASCOUT,  
MULTSIGNOUT} output  
TDSPCKO_{P, CARRYOUT}_ADREG_MULT  
CLK (ADREG) to {P,  
CARRYOUT} output  
2.79 3.16  
2.87 3.26  
3.72  
3.84  
3.72  
3.84  
4.32  
4.51  
ns  
ns  
TDSPCKO_{PCOUT, CARRYCASCOUT,  
MULTSIGNOUT}_ADREG_MULT  
CLK (ADREG) to {PCOUT,  
CARRYCASCOUT,  
MULTSIGNOUT} output  
Clock to Outs from Input Register Clock to Output Pins  
TDSPCKO_{P, CARRYOUT}_{AREG, BREG}_MULT CLK (AREG, BREG) to {P,  
3.97 4.52  
1.70 1.93  
5.36  
2.27  
5.36  
2.27  
6.20  
2.65  
ns  
ns  
CARRYOUT} output using  
multiplier  
TDSPCKO_{P, CARRYOUT}_{AREG, BREG}  
CLK (AREG, BREG) to {P,  
CARRYOUT} output not using  
multiplier  
TDSPCKO_{P, CARRYOUT}_CREG  
CLK (CREG) to {P, CARRYOUT} 1.70 1.93  
output  
2.27  
5.25  
2.27  
5.25  
2.80  
6.07  
ns  
ns  
TDSPCKO_{P, CARRYOUT}_DREG_MULT  
CLK (DREG) to {P, CARRYOUT} 3.89 4.44  
output  
Clock to Outs from Input Register Clock to Cascading Output Pins  
TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG}  
CLK (AREG, BREG) to {P,  
CARRYOUT} output  
0.66 0.76  
0.89  
5.49  
0.89  
5.49  
1.01  
6.39  
ns  
ns  
TDSPCKO_{PCOUT, CARRYCASCOUT,  
MULTSIGNOUT}_{AREG, BREG}_MULT  
CLK (AREG, BREG) to {PCOUT, 4.05 4.63  
CARRYCASCOUT,  
MULTSIGNOUT} output using  
multiplier  
TDSPCKO_{PCOUT, CARRYCASCOUT,  
MULTSIGNOUT}_{AREG, BREG}  
CLK (AREG, BREG) to {PCOUT, 1.79 2.03  
CARRYCASCOUT,  
MULTSIGNOUT} output not  
using multiplier  
2.40  
5.38  
2.40  
2.40  
5.38  
2.40  
2.84  
6.26  
2.99  
ns  
ns  
ns  
TDSPCKO_{PCOUT, CARRYCASCOUT,  
MULTSIGNOUT}_DREG_MULT  
CLK (DREG) to {PCOUT,  
CARRYCASCOUT,  
MULTSIGNOUT} output using  
multiplier  
3.98 4.54  
1.78 2.03  
TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_CREG CLK (CREG) to {PCOUT,  
CARRYCASCOUT,  
MULTSIGNOUT} output  
DS152 (v3.6) March 18, 2014  
www.xilinx.com  
Product Specification  
48  
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