Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 67: Clock-Capable Clock Input to Output Delay With MMCM
Speed Grade
-2 -1
LVCMOS25 Clock-capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
Symbol
Description
Device
Units
-3
-1L
TICKOFMMCMCC
Clock-capable Clock Input and OUTFF
with MMCM
XC6VLX75T
2.22
2.24
2.24
2.24
2.25
N/A
N/A
2.23
N/A
2.25
2.35
2.27
N/A
N/A
N/A
N/A
N/A
N/A
2.38
2.39
2.40
2.40
2.42
2.43
2.42
2.38
2.30
2.41
2.51
2.43
2.41
2.39
2.40
N/A
2.63
2.65
2.65
2.65
2.65
2.68
2.69
2.65
2.57
2.67
2.78
2.69
2.68
2.65
2.65
2.68
2.65
2.57
2.72
2.74
2.75
2.75
2.76
2.80
2.79
2.73
2.66
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
N/A
N/A
N/A
2.74
2.75
2.80
2.73
2.66
2.38
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
56
XILINX [ XILINX, INC ]
