Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Virtex-6 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 65. Values are expressed in nanoseconds unless otherwise noted.
Table 65: Global Clock Input to Output Delay Without MMCM
Speed Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM.
TICKOF
Global Clock input and OUTFF without
MMCM
XC6VLX75T
4.91
4.89
5.02
5.02
5.30
N/A
N/A
5.40
N/A
5.18
5.20
5.38
N/A
N/A
N/A
N/A
N/A
N/A
5.32
5.33
5.46
5.46
5.75
6.02
6.26
5.85
6.01
5.63
5.66
5.84
6.03
5.33
5.46
N/A
5.88
6.00
6.13
6.13
6.43
6.72
6.97
6.54
6.71
6.30
6.34
6.53
6.71
6.00
6.13
6.72
6.54
6.71
6.02
6.13
6.27
6.27
6.37
6.60
6.87
6.49
6.61
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
N/A
N/A
N/A
6.13
6.27
6.60
6.49
6.61
5.85
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
DS152 (v3.6) March 18, 2014
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Product Specification
54
XILINX [ XILINX, INC ]
