Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 59: Configuration Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
Units
-3
6
-2
6
-1
6
-1L
7
TSMCKBY
CCLK to BUSY out in readback at 2.5V
CCLK to BUSY out in readback at 1.8V
Maximum Frequency with respect to nominal CCLK
ns, Max
ns, Max
6
6
6
7
FSMCCK
FRBCCK
100
100
100
100
100
100
70
60
MHz, Max
MHz, Max
Maximum Readback Frequency with respect to
nominal CCLK
FMCCKTOL
Frequency tolerance, master mode with
respect to nominal CCLK
55
55
55
60
%
Boundary-Scan Port Timing Specifications
TMS and TDI Setup time before TCK/ Hold time
TTAPTCK/TTCKTAP
3.0/2.0 3.0/2.0 3.0/2.0 4.0/2.0
ns, Min
after TCK
TTCKTDO
TCK falling edge to TDO output valid at 2.5V
TCK falling edge to TDO output valid at 1.8V
Maximum configuration TCK clock frequency
6
6
6
6
6
6
7
7
ns, Max
ns, Max
FTCK
66
15
66
15
66
15
33
15
MHz, Max
MHz, Min
FTCKB_MIN
Minimum boundary-scan TCK clock frequency
when using IEEE Std 1149.6 (AC-JTAG). Minimum
operating temperature for IEEE Std 1149.6 is 0°C.
FTCKB
Maximum boundary-scan TCK clock frequency
66
66
66
33
MHz, Max
BPI Master Flash Mode Programming Switching
(2)
TBPICCO
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B
outputs valid after CCLK rising edge at 2.5V
6
6
6
6
6
6
7
7
ns
ns
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B
outputs valid after CCLK rising edge at 1.8V
T
BPIDCC/TBPICCD
Setup/Hold on D[15:0] data input pins
4.0/0.0 4.0/0.0 4.0/0.0 5.0/0.0
ns
TINITADDR
Minimum period of initial ADDR[25:0] address
cycles
3
3
3
3
CCLK cycles
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPIDCCD DIN Setup/Hold before/after the rising CCLK edge 3.0/0.0 3.0/0.0 3.0/0.0 3.5/0.0
TSPICCM
ns
ns
ns
ns
ns
µs
MOSI clock to out at 2.5V
6
6
6
6
2
6
6
6
6
2
6
6
6
6
2
7
7
7
7
2
MOSI clock to out at 1.8V
TSPICCFC
FCS_B clock to out at 2.5V
FCS_B clock to out at 1.8V
T
FSINIT/TFSINITH
FS[2:0] to INIT_B rising edge Setup and Hold
CCLK Output (Master Modes)
TMCCKL
Master CCLK clock Low time duty cycle
45/55
45/55
45/55
45/55
45/55
45/55
40/60
40/60
%, Min/Max
%, Min/Max
TMCCKH
Master CCLK clock High time duty cycle
CCLK Input (Slave Modes)
TSCCKL
TSCCKH
Slave CCLK clock minimum Low time
Slave CCLK clock minimum High time
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns, Min
ns, Min
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
FDCK
Maximum frequency for DCLK
DADDR Setup/Hold
200
200
200
200
MHz
ns
TMMCMDCK_DADDR
TMMCMCKD_DADDR
/
1.25/
0.00
1.40/
0.00
1.63/
0.00
1.64/
0.00
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
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XILINX [ XILINX, INC ]
