Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
DSP48E1 Switching Characteristics
Table 58: DSP48E1 Switching Characteristics
Speed Grade
Symbol
Description
Units
-1
(XC)
-1
(XQ)
-3
-2
-1L
Setup and Hold Times of Data/Control Pins to the Input Register Clock
{A, ACIN, B, BCIN} input to
{A, B} register CLK
0.25/ 0.29/ 0.35/
0.27 0.30 0.34
0.36/ 0.46/
0.34 0.39
ns
T
T
/
DSPDCK_{A, ACIN; B, BCIN}_{AREG; BREG}
DSPCKD_{A, ACIN; B, BCIN}_{AREG; BREG}
C input to C register CLK
0.16/ 0.19/ 0.22/
0.20 0.22 0.24
0.25/ 0.33/
0.24 0.30
ns
ns
T
/T
DSPDCK_C_CREG DSPCKD_C_CREG
D input to D register CLK
0.07/ 0.10/ 0.15/
0.31 0.34 0.39
0.16/ 0.24/
0.39 0.45
T
/T
DSPDCK_D_DREG DSPCKD_D_DREG
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{A, ACIN, B, BCIN}_MREG_MULT
TDSPCKD_{A, ACIN, B, BCIN}_MREG_MULT
/
{A, ACIN, B, BCIN} input to
M register CLK
2.36/ 2.70/ 3.21/
0.04 0.04 0.04
3.21/ 3.66/
0.04 0.02
ns
ns
TDSPDCK_{A, D}_ADREG
/
{A, D} input to AD register CLK
1.24/ 1.42/ 1.69/
0.10 0.12 0.13
1.69/ 1.91/
0.13 0.16
TDSPCKD_{A, D}_ADREG
Setup and Hold Times of Data/Control Pins to the Output Register Clock
{A, ACIN, B, BCIN} input to
P register CLK using multiplier
3.83/ 4.37/ 5.20/
–0.13 –0.13 –0.13 –0.13 –0.24
5.20/ 5.94/
ns
T
T
/
DSPDCK_{A, ACIN, B, BCIN}_PREG_MULT
DSPCKD_{A, ACIN, B, BCIN}_PREG_MULT
D input to P register CLK
3.62/ 4.13/ 4.90/
–0.47 –0.47 –0.47 –0.47 –0.77
4.90/ 5.61/
ns
ns
T
/ T
DSPDCK_D_PREG_MULT DSPCKD_D_PREG_MULT
{A, ACIN, B, BCIN} input to
P register CLK not using
multiplier
1.59/ 1.81/ 2.15/ 2.15/ 2.44/
–0.13 –0.13 –0.13 –0.13 –0.24
T
T
/
DSPDCK_{A, ACIN, B, BCIN}_PREG
DSPCKD_{A, ACIN, B, BCIN}_PREG
C input to P register CLK
1.42/ 1.61/ 1.91/
–0.10 –0.10 –0.10 –0.10 –0.19
1.91/ 2.16/
ns
ns
T
/ T
DSPDCK_C_PREG DSPCKD_C_PREG
TDSPDCK_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG
TDSPCKD_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG
/
{PCIN, CARRYCASCIN,
MULTSIGNIN} input to
P register CLK
1.23/ 1.41/ 1.67/ 1.67/ 1.91/
–0.02 –0.02 –0.02 –0.02 –0.07
Setup and Hold Times of the CE Pins
{CEA; CEB} input to {A; B}
register CLK
0.14/ 0.17/ 0.22/
0.19 0.22 0.25
0.22/ 0.30/
0.25 0.28
ns
ns
ns
ns
ns
T
T
/
DSPDCK_{CEA; CEB}_{AREG; BREG}
DSPCKD_{CEA; CEB}_{AREG; BREG}
CEC input to C register CLK
CED input to D register CLK
CEM input to M register CLK
CEP input to P register CLK
0.15/ 0.18/ 0.24/
0.18 0.20 0.23
0.24/ 0.31/
0.23 0.26
T
T
T
T
/ T
DSPDCK_CEC_CREG DSPCKD_CEC_CREG
0.20/ 0.24/ 0.31/
0.12 0.13 0.14
0.31/ 0.43/
0.14 0.16
/ T
DSPDCK_CED_DREG DSPCKD_CED_DREG
0.16/ 0.20/ 0.26/
0.19 0.21 0.25
0.26/ 0.32/
0.25 0.28
/ T
DSPDCK_CEM_MREG DSPCKD_CEM_MREG
0.32/ 0.38/ 0.46/
0.02 0.02 0.03
0.46/ 0.54/
0.03 0.04
/ T
DSPDCK_CEP_PREG DSPCKD_CEP_PREG
Setup and Hold Times of the RST Pins
{RSTA, RSTB} input to {A, B}
register CLK
0.27/ 0.31/ 0.38/
0.17 0.19 0.22
0.38/ 0.41/
0.22 0.25
ns
ns
ns
ns
T
T
/
DSPDCK_{RSTA; RSTB}_{AREG; BREG}
DSPCKD_{RSTA; RSTB}_{AREG; BREG}
RSTC input to C register CLK
RSTD input to D register CLK
RSTM input to M register CLK
0.18/ 0.20/ 0.23/
0.08 0.08 0.09
0.23/ 0.27/
0.09 0.11
T
T
T
/ T
DSPDCK_RSTC_CREG DSPCKD_RSTC_CREG
0.28/ 0.32/ 0.38/
0.15 0.16 0.19
0.38/ 0.45/
0.19 0.21
/ T
DSPDCK_RSTD_DREG DSPCKD_RSTD_DREG
0.20/ 0.23/ 0.26/
0.24 0.26 0.30
0.26/ 0.29/
0.30 0.34
/ T
DSPDCK_RSTM_MREG DSPCKD_RSTM_MREG
DS152 (v3.6) March 18, 2014
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Product Specification
46
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