Spartan-3E FPGA Family: Functional Description
Also, in a multi-FPGA daisy-chain configuration of more
than two devices, all intermediate FPGAs between the first
and last devices must be Spartan-3E or Virtex-5 FPGAs.
The last FPGA in the chain can be from any Xilinx FPGA
family.
BPI Mode Interaction with Right and Bottom Edge
Global Clock Inputs
Some of the BPI mode configuration pins are shared with
global clock inputs along the right and bottom edges of the
device (Bank 1 and Bank 2, respectively). These pins are
not easily reclaimable for clock inputs after configuration,
especially if the FPGA application access the parallel NOR
Flash after configuration. Table 64 summarizes the shared
pins.
Table 64: Shared BPI Configuration Mode and Global
Buffer Input Pins
Device
Edge
Global Buffer
Input Pin
BPI Mode
Configuration Pin
GCLK0
GCLK2
RDWR_B
D2
GCLK3
D1
Bottom
GCLK12
GCLK13
GCLK14
GCLK15
RHCLK0
RHCLK1
RHCLK2
RHCLK3
RHCLK4
RHCLK5
RHCLK6
RHCLK7
D7
D6
D4
D3
A10
A9
A8
A7
Right
A6
A5
A4
A3
DS312 (v4.2) December 14, 2018
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Product Specification
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XILINX [ XILINX, INC ]
