Spartan-3E FPGA Family: Functional Description
configuration file, then subsequent reconfigurations using
the JTAG port will fail. Potential workarounds include setting
the mode pins for JTAG configuration (M[2:0] = <1:0:1>) or
offsetting the initial memory location in Flash by 0x2000.
Stepping 0 Limitations when Reprogramming via
JTAG if FPGA Set for BPI Configuration
The FPGA can always be reprogrammed via the JTAG port,
regardless of the mode pin (M[2:0]) settings. However,
Stepping 0 devices have a minor limitation. If a Stepping 0
FPGA is set to configure in BPI mode and the FPGA is
attached to a parallel memory containing a valid FPGA
Stepping 1 devices fully support JTAG configuration even
when the FPGA mode pins are set for BPI mode.
X-Ref Target - Figure 59
CCLK
D[7:0]
+1.2V
+1.2V
V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
I
VCC
VCCO_1
LDC0
V
VCCO_1
CE#
x8 or
x8/x16
Flash
LDC1
OE#
HDC
WE#
BYTE#
PROM
LDC2
Not available
in VQ100
package
D
A[16:0]
Slave
Parallel
Mode
DQ[15:7]
BPI Mode
VCCO_2
D[7:0]
VCCO_2
D[7:0]
V
V
‘0’
‘1’
A
M2
M1
M0
DQ[7:0]
A[n:0]
‘1’
‘1’
‘0’
M2
M1
M0
A[23:17]
GND
Spartan-3E
FPGA
Spartan-3E
FPGA
BUSY
CCLK
BUSY
CCLK
‘0’
‘0’
CSI_B
CSO_B
INIT_B
CSI_B
CSO_B
CSO_B
RDWR_B
‘0’
RDWR_B
INIT_B
2.5V
JTAG
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TDI
TMS
TCK
TDO
TMS
TCK
TMS
TCK
V
+2.5V
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_50_082009
Figure 59: Daisy-Chaining from BPI Flash Mode
parallel Flash pins. The programming access points are
highlighted in the gray boxes in Figure 58 and Figure 59.
In-System Programming Support
I
In a production application, the parallel Flash PROM is
The FPGA itself can also be used as a parallel Flash PROM
programmer during development and test phases. Initially,
an FPGA-based programmer is downloaded into the FPGA
via JTAG. Then the FPGA performs the Flash PROM
programming algorithms and receives programming data
from the host via the FPGA’s JTAG interface. See the
Embedded System Tools Reference Manual.
usually preprogrammed before it is mounted on the printed
circuit board. In-system programming support is available
from third-party boundary-scan tool vendors and from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the parallel Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the parallel Flash, in high-impedance (Hi-Z). If
the HSWAP input is Low, the I/Os have pull-up resistors to
Dynamically Loading Multiple Configuration
Images Using MultiBoot Option
the V
input on their respective I/O bank. The external
CCO
programming hardware then has direct access to the
For additional information, refer to the “Reconfiguration and
MultiBoot” chapter in UG332.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
92
XILINX [ XILINX, INC ]
