Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 61
+1.2V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
Slave
Parallel
Mode
VCCO_2
V
V
‘1’
‘1’
‘0’
M2
M1
M0
Intelligent
Download Host
V
Spartan-3E
FPGA
VCC
D[7:0]
D[7:0]
Configuration
Memory
BUSY
SELECT
BUSY
Source
CSI_B
RDWR_B
CCLK
CSO_B
READ/WRITE
CLOCK
INIT_B
- Internal memory
- Disk drive
- Over network
- Over RF link
PROG_B
DONE
VCCAUX
TDO
+2.5V
INIT_B
TDI
TMS
TCK
GND
+2.5V
- Microcontroller
- Processor
- Tester
PROG_B
DONE
GND
- Computer
PROG_B
Recommend
+2.5V
JTAG
open-drain
driver
TDI
TMS
TCK
TDO
DS312-2_52_082009
Figure 61: Slave Parallel Configuration Mode
Slave Parallel Mode
For additional information, refer to the “Slave Parallel
(SelectMAP) Mode” chapter in UG332.
The FPGA captures data on the rising CCLK edge. If the
CCLK frequency exceeds 50 MHz, then the host must also
monitor the FPGA’s BUSY output. If the FPGA asserts
BUSY High, the host must hold the data for an additional
clock cycle, until BUSY returns Low. If the CCLK frequency
is 50 MHz or below, the BUSY pin may be ignored but
actively drives during configuration.
In Slave Parallel mode (M[2:0] = <1:1:0>), an external host,
such as a microprocessor or microcontroller, writes
byte-wide configuration data into the FPGA, using a typical
peripheral interface as shown in Figure 61.
The external download host starts the configuration process
by pulsing PROG_B and monitoring that the INIT_B pin
goes High, indicating that the FPGA is ready to receive its
first data. The host asserts the active-Low chip-select signal
(CSI_B) and the active-Low Write signal (RDWR_B). The
host then continues supplying data and clock signals until
either the FPGA’s DONE pin goes High, indicating a
successful configuration, or until the FPGA’s INIT_B pin
goes Low, indicating a configuration error.
The configuration process requires more clock cycles than
indicated from the configuration file size. Additional clocks
are required during the FPGA’s start-up sequence,
especially if the FPGA is programmed to wait for selected
Digital Clock Managers (DCMs) to lock to their respective
clock inputs (see Start-Up, page 106).
If the Slave Parallel interface is only used to configure the
FPGA, never to read data back, then the RDWR_B signal
DS312 (v4.2) December 14, 2018
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Product Specification
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