Spartan-3E FPGA Family: Functional Description
After the FPGA configures itself using BPI mode from one
end of the parallel Flash PROM, then the FPGA can trigger
a MultiBoot event and reconfigure itself from the opposite
end of the parallel Flash PROM. MultiBoot is only available
when using BPI mode and only for applications with a single
Spartan-3E FPGA.
Figure 60 shows an example usage. At power up, the FPGA
loads itself from the attached parallel Flash PROM. In this
example, the M0 mode pin is Low so the FPGA starts at
address 0 and increments through the Flash PROM
memory locations. After the FPGA completes configuration,
the application initially loaded into the FPGA performs a
board-level or system test using FPGA logic. If the test is
successful, the FPGA then triggers a MultiBoot event,
causing the FPGA to reconfigure from the opposite end of
the Flash PROM memory. This second configuration
contains the FPGA application for normal operation.
By default, MultiBoot mode is disabled. To trigger a
MultiBoot event, assert a Low pulse lasting at least 300 ns
on the MultiBoot Trigger (MBT) input to the
STARTUP_SPARTAN3E library primitive. When the MBT
signal returns High after the 300 ns or longer pulse, the
FPGA automatically reconfigures from the opposite end of
the parallel Flash memory.
Similarly, the general FPGA application could trigger
another MultiBoot event at any time to reload the
diagnostics design, and so on.
X-Ref Target - Figure 60
Parallel Flash PROM
Parallel Flash PROM
FFFFFF
FFFFFF
General
FPGA
General
FPGA
Application
Application
STARTUP_SPARTAN3E
GSR
User Area
GTS
MBT
User Area
> 300 ns
CLK
Diagnostics
FPGA
Application
Diagnostics
FPGA
Application
Reconfigure
0
0
First Configuration
Second Configuration
DS312-2_51_103105
Figure 60: Use MultiBoot to Load Alternate Configuration Images
In another potential application, the initial design loaded into
the FPGA image contains a “golden” or “fail-safe”
configuration image, which then communicates with the
outside world and checks for a newer image. If there is a
new configuration revision and the new image verifies as
good, the “golden” configuration triggers a MultiBoot event
to load the new image.
When a MultiBoot event is triggered, the FPGA then again
drives its configuration pins as described in Table 59.
However, the FPGA does not assert the PROG_B pin. The
system design must ensure that no other device drives on
these same pins during the reconfiguration process. The
FPGA’s DONE, LDC[2:0], or HDC pins can temporarily
disable any conflicting drivers during reconfiguration.
Asserting the PROG_B pin Low overrides the MultiBoot
feature and forces the FPGA to reconfigure starting from the
end of memory defined by the mode pins, shown in
Table 58.
DS312 (v4.2) December 14, 2018
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Product Specification
93
XILINX [ XILINX, INC ]
