Spartan-3E FPGA Family: Functional Description
Voltage Compatibility
Table 52: Maximum ConfigRate Settings for Platform
Flash
The PROM’s V
supply must be either 3.3V for the
CCINT
Maximum
serial XCFxxS Platform Flash PROMs or 1.8V for the
serial/parallel XCFxxP PROMs.
Platform Flash
Part Number
I/O Voltage
ConfigRate
(VCCO_2, VCCO
)
Setting
V
The FPGA’s VCCO_2 supply input and the Platform
XCF01S
XCF02S
XCF04S
3.3V or 2.5V
1.8V
25
12
Flash PROM’s V
supply input must be the same
CCO
voltage, ideally +2.5V. Both devices also support 1.8V and
3.3V interfaces but the FPGA’s PROG_B and DONE pins
require special attention as they are powered by the FPGA’s
XCF08P
XCF16P
XCF32P
3.3V, 2.5V, or 1.8V
25
V
supply, nominally 2.5V. See application note
CCAUX
XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for
additional information.
Supported Platform Flash PROMs
Table 51 shows the smallest available Platform Flash
PROM to program one Spartan-3E FPGA. A multiple-FPGA
daisy-chain application requires a Platform Flash PROM
large enough to contain the sum of the various FPGA file
sizes.
Table 51: Number of Bits to Program a Spartan-3E
FPGA and Smallest Platform Flash PROM
Spartan-3E
FPGA
Number of
Configuration Bits
Smallest Available
Platform Flash
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
581,344
1,353,728
2,270,208
3,841,184
XCF01S
XCF02S
XCF04S
XCF04S
XCF08P
or 2 x XCF04S
XC3S1600E
5,969,696
The XC3S1600E requires an 8 Mbit PROM. Two solutions
are possible: either a single 8 Mbit XCF08P parallel/serial
PROM or two 4 Mbit XCF04S serial PROMs cascaded. The
two XCF04S PROMs use a 3.3V V
supply while the
CCINT
XCF08P requires a 1.8V V
supply. If the board does
CCINT
not already have a 1.8V supply available, the two cascaded
XCF04S PROM solution is recommended.
CCLK Frequency
In Master Serial mode, the FPGA’s internal oscillator
generates the configuration clock frequency. The FPGA
provides this clock on its CCLK output pin, driving the
PROM’s CLK input pin. The FPGA starts configuration at its
lowest frequency and increases its frequency for the
remainder of the configuration process if so specified in the
configuration bitstream. The maximum frequency is
specified using the ConfigRate bitstream generator option.
Table 52 shows the maximum ConfigRate settings,
approximately equal to MHz, for various Platform Flash
devices and I/O voltages. For the serial XCFxxS PROMs,
the maximum frequency also depends on the interface
voltage.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
73
XILINX [ XILINX, INC ]
