Spartan-3E FPGA Family: Functional Description
P
Similarly, the FPGA’s HSWAP pin must be Low to
available as full-featured user-I/O pin and is powered by the
VCCO_0 supply.
enable pull-up resistors on all user-I/O pins during
configuration or High to disable the pull-up resistors. The
HSWAP control must remain at a constant logic level
throughout FPGA configuration. After configuration, when
the FPGA’s DONE output goes High, the HSWAP pin is
The FPGA's DOUT pin is used in daisy-chain applications,
described later. In a single-FPGA application, the FPGA’s
DOUT pin is not used but is actively driving during the
configuration process.
Table 50: Serial Master Mode Connections
FPGA
Direction
Pin Name
Description
During Configuration
After Configuration
HSWAP
Input
User I/O Pull-Up Control. When Low during Drive at valid logic level
configuration, enables pull-up resistors in all throughout configuration.
I/O pins to respective I/O bank VCCO input.
User I/O
P
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA configuration M2 = 0, M1 = 0, M0 = 0. Sampled User I/O
mode. See Design Considerations for the
HSWAP, M[2:0], and VS[2:0] Pins.
when INIT_B goes High.
DIN
Input
Serial Data Input.
ReceivesserialdatafromPROM’s User I/O
D0 output.
CCLK
Output
Configuration Clock. Generated by FPGA
internal oscillator. Frequency controlled by
ConfigRate bitstream generator option. If
CCLK PCB trace is long or has multiple
connections, terminate this output to maintain
signal integrity. See CCLK Design
Considerations.
Drives PROM’s CLK clock input. User I/O
DOUT
INIT_B
Output
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this pin
connects to DIN input of the next
FPGA in the chain.
User I/O
Open-drain Initialization Indicator. Active Low. Goes
bidirectional Low at start of configuration during
Connects to PROM’s OE/RESET User I/O. If unused in
input. FPGA clears PROM’s
address counter at start of
configuration, enables outputs
during configuration. PROM also
holds FPGA in Initialization state
until PROM reaches Power-On
Reset (POR) state. If CRC error
detected during configuration,
FPGA drives INIT_B Low.
the application, drive
INIT_B High.
I/O
Initialization memory clearing process.
Released at end of memory clearing, when
mode select pins are sampled. Requires
external 4.7 kΩ pull-up resistor to VCCO_2.
DONE
Open-drain FPGA Configuration Done. Low during
bidirectional configuration. Goes High when FPGA
Connects to PROM’s chip-enable Pulled High via external
(CE) input. Enables PROM during pull-up. When High,
I/O
successfully completes configuration.
Requires external 330 Ω pull-up resistor to
2.5V.
configuration. Disables PROM
after configuration.
indicates that the FPGA
successfully
configured.
PROG_B
Input
Program FPGA. Active Low. When asserted Must be High during configuration Drive PROG_B Low
Low for 500 ns or longer, forces the FPGA to to allow configuration to start.
and release to
restart its configuration process by clearing
configuration memory and resetting the
DONE and INIT_B pins once PROG_B
returns High. Recommend external 4.7 kΩ
pull-up resistor to 2.5V. Internal pull-up value
may be weaker (see Table 78). If driving
externally with a 3.3V output, use an
open-drain or open-collector driver or use a
current limiting series resistor.
Connects to PROM’s CF pin,
allowing JTAG PROM
programming algorithm to
reprogram the FPGA.
reprogram FPGA.
DS312 (v4.2) December 14, 2018
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Product Specification
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