Spartan-3E FPGA Family: Functional Description
Flash PROM, as illustrated in Figure 51. The FPGA
supplies the CCLK output clock from its internal oscillator to
the attached Platform Flash PROM. In response, the
Platform Flash PROM supplies bit-serial data to the FPGA’s
DIN input, and the FPGA accepts this data on each rising
CCLK edge.
Master Serial Mode
For additional information, refer to the “Master Serial Mode”
chapter in UG332.
In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E
FPGA configures itself from an attached Xilinx Platform
X-Ref Target - Figure 51
+1.2V
XCFxxS = +3.3V
XCFxxP = +1.8V
V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCINT
VCCO_2
DIN
V
D0
VCCO
V
Serial Master
Mode
CCLK
DOUT
INIT_B
CLK
‘0’
‘0’
‘0’
M2
M1
M0
OE/RESET
+2.5V
Platform Flash
Spartan-3E
XCFxx
FPGA
CE
CF
CEO
+2.5V
JTAG
VCCAUX
+2.5V
VCCJ
TDO
+2.5V
TDI
TDI
TDO
TDI
TMS
TCK
TDO
TMS
TCK
TMS
TCK
GND
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_44_082009
Figure 51: Master Serial Mode using Platform Flash PROM
All mode select pins, M[2:0], must be Low when sampled,
when the FPGA’s INIT_B output goes High. After
configuration, when the FPGA’s DONE output goes High,
the mode select pins are available as full-featured user-I/O
pins.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
71
XILINX [ XILINX, INC ]
