Spartan-3E FPGA Family: Functional Description
Table 46: Pin Behavior during Configuration (Cont’d)
SPI (Serial
Flash)
BPI (Parallel
NOR Flash)
Pin Name
Master Serial
JTAG
Slave Parallel Slave Serial
I/O Bank(3)
D0/DIN
RDWR_B
A23
DIN
DIN
D0
D0
DIN
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RDWR_B
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
RDWR_B
A22
A21
A20
A19/VS2
A18/VS1
A17/VS0
A16
VS2
VS1
VS0
A15
A14
A13
A12
A11
A10
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
LDC0
LDC1
LDC2
HDC
LDC0
LDC1
LDC2
HDC
Notes:
1. Gray shaded cells represent pins that are in a high-impedance state (Hi-Z, floating) during configuration. These pins have an optional
internal pull-up resistor to their respective VCCO supply pin that is active throughout configuration if the HSWAP input is Low.
2. Yellow shaded cells represent pins with an internal pull-up resistor to its respective voltage supply rail that is active during
configuration, regardless of the HSWAP pin.
3. Note that dual-purpose outputs are supplied by VCCO, and configuration inputs are supplied by VCCAUX
.
The HSWAP pin itself has a pull-up resistor enabled during
configuration. However, the VCCO_0 supply voltage must
be applied before the pull-up resistor becomes active. If the
VCCO_0 supply ramps after the VCCO_2 power supply, do
not let HSWAP float; tie HSWAP to the desired logic level
externally.
Table 47 shows the default I/O standard setting for the
various configuration pins during the configuration process.
The configuration interface is designed primarily for 2.5V
operation when the VCCO_2 (and VCCO_1 in BPI mode)
connects to 2.5V.
Table 47: Default I/O Standard Setting During Config-
Spartan-3E FPGAs have only six dedicated configuration
pins, including the DONE and PROG_B pins, and the four
JTAG boundary-scan pins: TDI, TDO, TMS, and TCK. All
other configuration pins are dual-purpose I/O pins and are
available to the FPGA application after the DONE pin goes
High. See Start-Up for additional information.
uration (VCCO_2 = 2.5V)
Pin(s)
I/O Standard Output Drive Slew Rate
8 mA Slow
All, including CCLK LVCMOS25
DS312 (v4.2) December 14, 2018
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Product Specification
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XILINX [ XILINX, INC ]
