Spartan-3E FPGA Family: Functional Description
Table 49: Pull-up or Pull-down Values for HSWAP, M[2:0], and VS[2:0]
Required Resistor Value to Define Logic Level on
HSWAP, M[2:0], or VS[2:0]
I/O Pull-up Resistors
during Configuration
HSWAP Value
High
Low
0
Enabled
Pulled High via an internal pull-up
resistor to the associated VCCO
supply. No external pull-up resistor is
necessary.
Pulled Low using an appropriately sized
pull-down resistor to GND.
For a 2.5V or 3.3V interface: R ≤ 560Ω . For a
1.8V interface: R ≤ 1.1kΩ .
1
Disabled
Pulled High using a 3.3 to 4.7kΩ
resistor to the associated VCCO
supply.
Pulled Low using a 3.3 to 4.7kΩ resistor to
GND.
The logic level on HSWAP dictates how to define the logic
levels on M[2:0] and VS[2:0], as shown in Table 49. If the
application requires HSWAP to be High, the HSWAP pin is
pulled High using an external 3.3kΩ to 4.7kΩ resistor to
VCCO_0. If the application requires HSWAP to be Low
during configuration, then HSWAP is either connected to
GND or pulled Low using an appropriately sized external
pull-down resistor to GND. When HSWAP is Low, its pin has
an internal pull-up resistor to VCCO_0. The external
pull-down resistor must be strong enough to define a logic
Low on HSWAP for the I/O standard used during
configuration. For 2.5V or 3.3V I/O, the pull-down resistor is
560Ω or lower. For 1.8V I/O, the pull-down resistor is 1.1kΩ
or lower.
Once HSWAP is defined, use Table 49 to define the logic
values for M[2:0] and VS[2:0].
Use the weakest external pull-up or pull-down resistor value
allowed by the application. The resistor must be strong
enough to define a logic Low or High during configuration.
However, when driving the HSWAP, M[2:0], or VS[2:0] pins
after configuration, the output driver must be strong enough
to overcome the pull-up or pull-down resistor value and
generate the appropriate logic levels. For example, to
overcome a 560Ω pull-down resistor, a 3.3V FPGA I/O pin
must use a 6 mA or stronger driver.
DS312 (v4.2) December 14, 2018
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Product Specification
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