Spartan-3E FPGA Family: Functional Description
product ranging from –17,179,738,112 to
10
Dedicated Multipliers
For additional information, refer to the “Using Embedded
Multipliers” chapter in UG331.
+17,179,869,184 .
10
Implement multipliers with inputs less than 18 bits by
sign-extending the inputs (i.e., replicating the
The Spartan-3E devices provide 4 to 36 dedicated multiplier
blocks per device. The multipliers are located together with
the block RAM in one or two columns depending on device
density. See Arrangement of RAM Blocks on Die for details
on the location of these blocks and their connectivity.
most-significant bit). Wider multiplication operations are
performed by combining the dedicated multipliers and
slice-based logic in any viable combination or by
time-sharing a single multiplier. Perform unsigned
multiplication by restricting the inputs to the positive range.
Tie the most-significant bit Low and represent the unsigned
value in the remaining 17 lesser-significant bits.
Operation
The multiplier blocks primarily perform two’s complement
numerical multiplication but can also perform some less
obvious applications, such as simple data storage and
barrel shifting. Logic slices also implement efficient small
multipliers and thereby supplement the dedicated
multipliers. The Spartan-3E dedicated multiplier blocks
have additional features beyond those provided in
Spartan-3 FPGAs.
Optional Pipeline Registers
As shown in Figure 36, each multiplier block has optional
registers on each of the multiplier inputs and the output. The
registers are named AREG, BREG, and PREG and can be
used in any combination. The clock input is common to all
the registers within a block, but each register has an
independent clock enable and synchronous reset controls
making them ideal for storing data samples and coefficients.
When used for pipelining, the registers boost the multiplier
clock rate, beneficial for higher performance applications.
Each multiplier performs the principle operation P = A × B,
where ‘A’ and ‘B’ are 18-bit words in two’s complement
form, and ‘P’ is the full-precision 36-bit product, also in two’s
complement form. The 18-bit inputs represent values
ranging from –131,072 to +131,071 with a resulting
Figure 36 illustrates the principle features of the multiplier
block.
10
10
X-Ref Target - Figure 36
AREG
(Optional)
CEA
CE
A[17:0]
D
Q
PREG
(Optional)
RST
CEP
CE
D
RSTA
Q
P[35:0]
X
BREG
(Optional)
RST
CEB
CE
RSTP
B[17:0]
D
Q
RST
RSTB
CLK
DS312-2_27_021205
Figure 36: Principle Ports and Functions of Dedicated Multiplier Blocks
Use the MULT18X18SIO primitive shown in Figure 37 to
instantiate a multiplier within a design. Although high-level
logic synthesis software usually automatically infers a
multiplier, adding the pipeline registers might require the
MULT18X18SIO primitive. Connect the appropriate signals
to the MULT18X18SIO multiplier ports and set the individual
AREG, BREG, and PREG attributes to ‘1’ to insert the
associated register, or to 0 to remove it and make the signal
path combinatorial.
DS312 (v4.2) December 14, 2018
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Product Specification
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