Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 37
Cascading Multipliers
MULT18X18SIO
The MULT18X18SIO primitive has two additional ports
called BCIN and BCOUT to cascade or share the
A[17:0]
B[17:0]
CEA
P[35:0]
multiplier’s ‘B’ input among several multiplier bocks. The
18-bit BCIN “cascade” input port offers an alternate input
source from the more typical ‘B’ input. The B_INPUT
attribute specifies whether the specific implementation uses
the BCIN or ‘B’ input path. Setting B_INPUT to DIRECT
chooses the ‘B’ input. Setting B_INPUT to CASCADE
selects the alternate BCIN input. The BREG register then
optionally holds the selected input value, if required.
CEB
CEP
CLK
RSTA
RSTB
RSTP
BCOUT is an 18-bit output port that always reflects the
value that is applied to the multiplier’s second input, which is
either the ‘B’ input, the cascaded value from the BCIN input,
or the output of the BREG if it is inserted.
BCIN[17:0]
BCOUT[17:0]
DS312-2_28_021205
Figure 37: MULT18X18SIO Primitive
Figure 38 illustrates the four possible configurations using
different settings for the B_INPUT attribute and the BREG
attribute.
X-Ref Target - Figure 38
BCOUT[17:0]
BCOUT[17:0]
BREG
CE
X
X
CEB
D
Q
BREG = 0
CLK
B_INPUT = CASCADE
RST
BREG = 1
B_INPUT = CASCADE
RSTB
BCIN[17:0]
BCIN[17:0]
BCOUT[17:0]
BCOUT[17:0]
BREG
X
X
CEB
CE
D
B[17:0]
B[17:0]
Q
BREG = 0
B_INPUT = DIRECT
CLK
RST
BREG = 1
B_INPUT = DIRECT
RSTB
DS312-2_29_021505
Figure 38: Four Configurations of the B Input
DS312 (v4.2) December 14, 2018
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