Spartan-3E FPGA Family: Functional Description
Table 7: Differential IOSTANDARD Bank Compatibility
VCCO Supply
Input
Differential
IOSTANDARD
Differential Bank
Requirements:
Restriction(1)
1.8V
2.5V
3.3V
VREF
Input,
On-chip Differential Termination,
Output
Applies to Outputs
LVDS_25
Input
Input
Only
Input,
On-chip Differential Termination,
Output
Applies to Outputs
RSDS_25
Input
Input
Input
Only
Input,
On-chip Differential Termination,
Output
Applies to Outputs
MINI_LVDS_25
Input
Only
LVPECL_25
BLVDS_25
Input
Input
Input
Input
VREF is not used for
these I/O standards
Input,
Output
Input
Input,
Output
NoDifferentialBank
Input
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
Input
Input
Input
Restriction
(other I/O bank
restrictions might
Input,
Output
Input
apply)
Input,
Output
Input
Input,
Output
DIFF_SSTL2_I
Input
Input
Notes:
1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.
HSTL and SSTL inputs use the Reference Voltage (V
bias the input-switching threshold. Once a configuration
) to
On-Chip Differential Termination
REF
Spartan-3E devices provide an on-chip ~120Ω differential
termination across the input differential receiver terminals.
The on-chip input differential termination in Spartan-3E
devices potentially eliminates the external 100Ω termination
resistor commonly found in differential receiver circuits.
Differential termination is used for LVDS, mini-LVDS, and
RSDS as applications permit.
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use HSTL/SSTL, a few specifically reserved
I/O pins on the same bank automatically convert to V
REF
inputs. For banks that do not contain HSTL or SSTL, V
pins remain available for user I/Os or input pins.
REF
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling
properties (for example, Common-Mode Rejection) of these
standards permit exceptionally high data transfer rates. This
subsection introduces the differential signaling capabilities
of Spartan-3E devices.
On-chip Differential Termination is available in banks with
V
= 2.5V and is not supported on dedicated input pins.
CCO
Set the DIFF_TERM attribute to TRUE to enable Differential
Termination on a differential I/O pin pair.
The DIFF_TERM attribute uses the following syntax in the
UCF file:
Each device-package combination designates specific I/O
pairs specially optimized to support differential standards. A
unique L-number, part of the pin name, identifies the
line-pairs associated with each bank (see Module 4, Pinout
Descriptions). For each pair, the letters P and N designate
the true and inverted lines, respectively. For example, the
pin names IO_L43P_3 and IO_L43N_3 indicate the true
and inverted lines comprising the line pair L43 on Bank 3.
INST <I/O_BUFFER_INSTANTIATION_NAME>
DIFF_TERM = "<TRUE/FALSE>";
V
provides current to the outputs and additionally
CCO
powers the On-Chip Differential Termination. V
must be
CCO
2.5V when using the On-Chip Differential Termination. The
lines are not required for differential operation.
V
REF
To further understand how to combine multiple
IOSTANDARDs within a bank, refer to IOBs Organized into
Banks, page 19.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
17
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