Spartan-3E FPGA Family: Functional Description
1. All V
pins must be connected within a bank.
IOBs Organized into Banks
REF
REF
2. All V
lines associated with the bank must be set to
The Spartan-3E architecture organizes IOBs into four I/O
banks as shown in Figure 13. Each bank maintains
the same voltage level.
3. The V
levels used by all standards assigned to the
separate V
and V
supplies. The separate supplies
REF
CCO
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Inputs of the bank must agree. The Xilinx development
software checks for this. Table 6 describes how different
standards use the V
allow each bank to independently set V
. Similarly, the
CCO
V
supplies can be set for each bank. Refer to Table 6
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supply.
and Table 7 for V
and V
requirements.
REF
CCO
REF
If V
is not required to bias the input switching thresholds,
When working with Spartan-3E devices, most of the
differential I/O standards are compatible and can be
combined within any given bank. Each bank can support
any two of the following differential standards: LVDS_25
outputs, MINI_LVDS_25 outputs, and RSDS_25 outputs. As
an example, LVDS_25 outputs, RSDS_25 outputs, and any
other differential inputs while using on-chip differential
termination are a valid combination. A combination not
allowed is a single bank with LVDS_25 outputs, RSDS_25
outputs, and MINI_LVDS_25 outputs.
REF
all associated V
user I/Os or input pins.
pins within the bank can be used as
REF
Package Footprint Compatibility
Sometimes, applications outgrow the logic capacity of a
specific Spartan-3E FPGA. Fortunately, the Spartan-3E
family is designed so that multiple part types are available in
pin-compatible package footprints, as described in
Module 4, Pinout Descriptions. In some cases, there are
subtle differences between devices available in the same
footprint. These differences are outlined for each package,
such as pins that are unconnected on one device but
connected on another in the same package or pins that are
dedicated inputs on one package but full I/O on another.
When designing the printed circuit board (PCB), plan for
potential future upgrades and package migration.
X-Ref Target - Figure 13
Bank 0
The Spartan-3E family is not pin-compatible with any
previous Xilinx FPGA family.
Bank 2
Dedicated Inputs
DS312-2_26_021205
Dedicated Inputs are IOBs used only as inputs. Pin names
designate a Dedicated Input if the name starts with IP, for
example, IP or IP_Lxxx_x. Dedicated inputs retain the full
functionality of the IOB for input functions with a single
exception for differential inputs (IP_Lxxx_x). For the
differential Dedicated Inputs, the on-chip differential
termination is not available. To replace the on-chip
differential termination, choose a differential pair that
supports outputs (IO_Lxxx_x) or use an external 100Ω
termination resistor on the board.
Figure 13: Spartan-3E I/O Banks (top view)
I/O Banking Rules
When assigning I/Os to banks, these V
followed:
rules must be
CCO
1. All V
pins on the FPGA must be connected even if a
CCO
bank is unused.
2. All V
lines associated within a bank must be set to
CCO
the same voltage level.
ESD Protection
3. The V
levels used by all standards assigned to the
CCO
I/Os of any given bank must agree. The Xilinx
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: one diode
development software checks for this. Table 6 and
Table 7 describe how different standards use the V
supply.
CCO
extends P-to-N from the pad to V
and a second diode
CCO
4. If a bank does not have any V
requirements,
CCO
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
of the signal standard selected. The presence of diodes
limits the ability of Spartan-3E I/Os to tolerate high signal
connect V
to an available voltage, such as 2.5V or
CCO
3.3V. Some configuration modes might place additional
requirements. Refer to Configuration for more
V
CCO
information.
voltages. The V absolute maximum rating in Table 73 of
Module 3, DC and Switching Characteristics specifies the
voltage range that I/Os can tolerate.
IN
If any of the standards assigned to the Inputs of the bank
use V
, then the following additional rules must be
REF
observed:
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
19
XILINX [ XILINX, INC ]
