Spartan-3E FPGA Family: Functional Description
beginning of design operation in the User mode. After the
GTS net is released, all user I/Os go active while all unused
I/Os are pulled down (PULLDOWN). The designer can
control how the unused I/Os are terminated after GTS is
released by setting the Bitstream Generator (BitGen) option
UnusedPin to PULLUP, PULLDOWN, or FLOAT.
Supply Voltages for the IOBs
The IOBs are powered by three supplies:
1. The V
supplies, one for each of the FPGA’s I/O
CCO
banks, power the output drivers. The voltage on the
pins determines the voltage swing of the output
V
CCO
signal.
One clock cycle later (default), the Global Write Enable
(GWE) net is released allowing the RAM and registers to
change states. Once in User mode, any pull-up resistors
enabled by HSWAP revert to the user settings and HSWAP
is available as a general-purpose I/O. For more information
on PULLUP and PULLDOWN, see Pull-Up and Pull-Down
Resistors.
2.
3.
V
is the main power supply for the FPGA’s internal
CCINT
logic.
V
is an auxiliary source of power, primarily to
CCAUX
optimize the performance of various FPGA functions
such as I/O switching.
I/O and Input-Only Pin Behavior During
Power-On, Configuration, and User Mode
Behavior of Unused I/O Pins After
Configuration
In this section, all behavior described for I/O pins also
applies to input-only pins and dual-purpose I/O pins that are
not actively involved in the currently-selected configuration
mode.
By default, the Xilinx ISE development software
automatically configures all unused I/O pins as input pins
with individual internal pull-down resistors to GND.
This default behavior is controlled by the UnusedPin
bitstream generator (BitGen) option, as described in
Table 69.
All I/O pins have ESD clamp diodes to their respective V
CCO
CCINT
supply and from GND, as shown in Figure 5. The V
(1.2V), V (2.5V), and V supplies can be applied in
CCAUX
CCO
any order. Before the FPGA can start its configuration
process, V , V Bank 2, and V must have
JTAG Boundary-Scan Capability
CCINT
CCO
CCAUX
reached their respective minimum recommended operating
levels indicated in Table 74. At this time, all output drivers
All Spartan-3E IOBs support boundary-scan testing
compatible with IEEE 1149.1/1532 standards. During
boundary-scan operations such as EXTEST and HIGHZ the
pull-down resistor is active. See JTAG Mode for more
information on programming via JTAG.
are in a high-impedance state. V
Bank 2, V
, and
CCO
CCINT
V
serve as inputs to the internal Power-On Reset
CCAUX
circuit (POR).
A Low level applied to the HSWAP input enables pull-up
resistors on user-I/O and input-only pins from power-on
throughout configuration. A High level on HSWAP disables
the pull-up resistors, allowing the I/Os to float. HSWAP
contains an internal pull-up resistor and defaults to High if
left floating. As soon as power is applied, the FPGA begins
initializing its configuration memory. At the same time, the
FPGA internally asserts the Global Set-Reset (GSR), which
asynchronously resets all IOB storage elements to a default
Low state. Also see Pin Behavior During Configuration.
Upon the completion of initialization and the beginning of
configuration, INIT_B goes High, sampling the M0, M1, and
M2 inputs to determine the configuration mode.
Configuration data is then loaded into the FPGA. The I/O
drivers remain in a high-impedance state (with or without
pull-up resistors, as determined by the HSWAP input)
throughout configuration.
At the end of configuration, the GSR net is released, placing
the IOB registers in a Low state by default, unless the
loaded design reverses the polarity of their respective SR
inputs.
The Global Three State (GTS) net is released during
Start-Up, marking the end of configuration and the
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
20
XILINX [ XILINX, INC ]
