Spartan-3E FPGA Family: Functional Description
X-Ref Target
-
Figure 11
X-Ref Target - Figure 12
Spartan-3E
Differential
Output
Spartan-3E
Differential Input
Z
= 50Ω
0
Pull-up
Output Path
Input Path
Z
Z
= 50Ω
= 50Ω
0
Spartan-3E
Differential Input
with On-Chip
Differential
Keeper
Pull-down
Spartan-3E
Differential
Output
0
Terminator
DS312-2_25_020807
Figure 12: Keeper Circuit
Z
= 50Ω
0
Slew Rate Control and Drive Strength
DS312-2_24_082605
Each IOB has a slew-rate control that sets the output
switching edge-rate for LVCMOS and LVTTL outputs. The
SLEW attribute controls the slew rate and can either be set
to SLOW (default) or FAST.
Figure 11: Differential Inputs and Outputs
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors inside each IOB optionally
force a floating I/O or Input-only pin to a determined state.
Pull-up and pull-down resistors are commonly applied to
unused I/Os, inputs, and three-state outputs, but can be
used on any I/O or Input-only pin. The pull-up resistor
Each LVCMOS and LVTTL output additionally supports up
to six different drive current strengths as shown in Table 8.
To adjust the drive strength for each output, the DRIVE
attribute is set to the desired drive strength: 2, 4, 6, 8, 12,
and 16. Unless otherwise specified in the FPGA application,
the software default IOSTANDARD is LVCMOS25, SLOW
slew rate, and 12 mA output drive.
connects an IOB to V
through a resistor. The resistance
CCO
value depends on the V
voltage (see Module 3, DC and
CCO
Switching Characteristics for the specifications). The
pull-down resistor similarly connects an IOB to ground with
a resistor. The PULLUP and PULLDOWN attributes and
library primitives turn on these optional resistors.
Table 8: Programmable Output Drive Current
Output Drive Current (mA)
IOSTANDARD
2
4
✔
✔
✔
✔
✔
-
6
✔
✔
✔
✔
✔
-
8
✔
✔
✔
✔
-
12
✔
✔
✔
-
16
✔
✔
-
By default, PULLDOWN resistors terminate all unused I/O
and Input-only pins. Unused I/O and Input-only pins can
alternatively be set to PULLUP or FLOAT. To change the
unused I/O Pad setting, set the Bitstream Generator
(BitGen) option UnusedPin to PULLUP, PULLDOWN, or
FLOAT. The UnusedPin option is accessed through the
Properties for Generate Programming File in ISE. See
Bitstream Generator (BitGen) Options.
LVTTL
✔
✔
✔
✔
✔
✔
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
-
-
-
-
-
-
During configuration a Low logic level on the HSWAP pin
activates pull-up resistors on all I/O and Input-only pins not
actively used in the selected configuration mode.
High output current drive strength and FAST output slew
rates generally result in fastest I/O performance. However,
these same settings generally also result in transmission
line effects on the printed circuit board (PCB) for all but the
shortest board traces. Each IOB has independent slew rate
and drive strength controls. Use the slowest slew rate and
lowest output drive current that meets the performance
requirements for the end application.
Keeper Circuit
Each I/O has an optional keeper circuit (see Figure 12) that
keeps bus lines from floating when not being actively driven.
The KEEPER circuit retains the last logic level on a line after
all drivers have been turned off. Apply the KEEPER
attribute or use the KEEPER library primitive to use the
KEEPER circuitry. Pull-up and pull-down resistors override
the KEEPER settings.
Likewise, due to lead inductance, a given package supports
a limited number of simultaneous switching outputs (SSOs)
when using fast, high-drive outputs. Only use fast,
high-drive outputs when required by the application.
DS312 (v4.2) December 14, 2018
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Product Specification
18
XILINX [ XILINX, INC ]
