Spartan-3E FPGA Family: Functional Description
Storage Element Functions
There are three pairs of storage elements in each IOB, one
pair for each of the three paths. It is possible to configure
each of these storage elements as an edge-triggered
D-type flip-flop (FD) or a level-sensitive latch (LD).
synchronized to the clock signal’s rising edge and
converting it to bits synchronized on both the rising and the
falling edge. The combination of two registers and a
multiplexer is referred to as a Double-Data-Rate D-type
flip-flop (ODDR2).
The storage-element pair on either the Output path or the
Three-State path can be used together with a special
multiplexer to produce Double-Data-Rate (DDR)
transmission. This is accomplished by taking data
Table 4 describes the signal paths associated with the
storage element.
Table 4: Storage Element Signal Description
Storage
Element
Signal
Description
Data input
Function
D
Data at this input is stored on the active edge of CK and enabled by CE. For latch operation when
the input is enabled, data passes directly to the output Q.
Q
Data output
The data on this output reflects the state of the storage element. For operation as a latch in
transparent mode, Q mirrors the data at D.
CK
CE
SR
Clock input
Data is loaded into the storage element on this input’s active edge with CE asserted.
When asserted, this input enables CK. If not connected, CE defaults to the asserted state.
Clock Enable input
Set/Reset input
This input forces the storage element into the state specified by the SRHIGH/SRLOW attributes.
The SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.
If both SR and REV are active at the same time, the storage element gets a value of 0.
REV
Reverse input
This input is used together with SR. It forces the storage element into the state opposite from what
SR does. The SYNC/ASYNC attribute setting determines whether the REV input is synchronized
to the clock or not. If both SR and REV are active at the same time, the storage element gets a
value of 0.
As shown in Figure 5, the upper registers in both the output
and three-state paths share a common clock. The OTCLK1
clock signal drives the CK clock inputs of the upper registers
on the output and three-state paths. Similarly, OTCLK2
drives the CK inputs for the lower registers on the output
and three-state paths. The upper and lower registers on the
input path have independent clock lines: ICLK1 and ICLK2.
controls the CE inputs for the register pair on the three-state
path and ICE does the same for the register pair on the
input path.
The Set/Reset (SR) line entering the IOB controls all six
registers, as is the Reverse (REV) line.
In addition to the signal polarity controls described in IOB
Overview, each storage element additionally supports the
controls described in Table 5.
The OCE enable line controls the CE inputs of the upper
and lower registers on the output path. Similarly, TCE
Table 5: Storage Element Options
Option Switch
FF/Latch
Function
Specificity
Chooses between an edge-triggered flip-flop or a
level-sensitive latch
Independent for each storage element
SYNC/ASYNC
Determines whether the SR set/reset control is
synchronous or asynchronous
Independent for each storage element
SRHIGH/SRLOW
Determines whether SR acts as a Set, which forces Independent for each storage element, except when using
the storage element to a logic 1 (SRHIGH) or a
Reset, which forces a logic 0 (SRLOW)
ODDR2. In the latter case, the selection for the upper
element will apply to both elements.
INIT1/INIT0
When Global Set/Reset (GSR) is asserted or after
configuration this option specifies the initial state of ODDR2, which uses two IOBs. In the ODDR2 case,
Independent for each storage element, except when using
the storage element, either set (INIT1) or reset
(INIT0). By default, choosing SRLOW also selects
INIT0; choosing SRHIGH also selects INIT1.
selecting INIT0 for one IOBs applies to both elements
within the IOB, although INIT1 could be selected for the
elements in the other IOB.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
13
XILINX [ XILINX, INC ]
