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XC3S500E-4FTG256CS1 参数 Datasheet PDF下载

XC3S500E-4FTG256CS1图片预览
型号: XC3S500E-4FTG256CS1
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 572MHz, 10476-Cell, CMOS, PBGA256,]
分类和应用: 时钟可编程逻辑
文件页数/大小: 227 页 / 6528 K
品牌: XILINX [ XILINX, INC ]
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Spartan-3E FPGA Family: Functional Description  
Spartan-3E FPGAs provide additional input flexibility by  
allowing I/O standards to be mixed in different banks. For a  
IOSTANDARDs that can be combined and if the  
IOSTANDARD is supported as an input only or can be used  
for both inputs and outputs.  
particular V  
voltage, Table 6 and Table 7 list all of the  
CCO  
Table 6: Single-Ended IOSTANDARD Bank Compatibility  
VCCO Supply/Compatibility  
Input Requirements  
Board  
Single-Ended  
IOSTANDARD  
1.2V  
1.5V  
1.8V  
2.5V  
3.3V  
VREF  
Termination  
Voltage (VTT  
)
Input/  
Output  
LVTTL  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N/R(1)  
N/R  
N/R  
N/R  
N/R  
N/R  
N/R  
N/R  
0.9  
N/R  
Input/  
Output  
LVCMOS33  
LVCMOS25  
LVCMOS18  
LVCMOS15  
LVCMOS12  
PCI33_3  
N/R  
N/R  
N/R  
N/R  
N/R  
N/R  
N/R  
0.9  
Input/  
Output  
Input  
Input  
Input  
Input  
Input/  
Output  
Input  
Input  
Input  
-
Input/  
Output  
Input  
Input/  
Output  
Input  
Input  
Input/  
Output  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Input/  
Output  
PCI66_3  
-
Input/  
Output  
HSTL_I_18  
HSTL_III_18  
SSTL18_I  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input/  
Output  
1.1  
1.8  
Input/  
Output  
0.9  
0.9  
Input/  
Output  
SSTL2_I  
-
1.25  
1.25  
Notes:  
1. N/R - Not required for input operation.  
DS312 (v4.2) December 14, 2018  
www.xilinx.com  
Product Specification  
16  
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