Spartan-3E FPGA Family: Pinout Descriptions
Table 154: User I/Os Per Bank for the XC3S1600E in the FG484 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
(2)
I/O
56
INPUT
DUAL
1
VREF(1)
CLK
Top
0
1
2
3
94
94
22
16
18
16
72
7
7
8
Right
50
21
24
0
0(2)
0(2)
8
Bottom
Left
94
45
7
94
63
7
TOTAL
376
214
46
28
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Footprint Migration Differences
The XC3S1600E FPGA is the only Spartan-3E device
offered in the FG484 package.
DS312 (v4.2) December 14, 2018
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Product Specification
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XILINX [ XILINX, INC ]
