Spartan-3E FPGA Family: Pinout Descriptions
Table 132: CP132 Package Pinout (Cont’d)
XC3S250E
XC3S500E
Pin Name
XC3S100E
Pin Name
Bank
CP132 Ball
Type
2
2
2
N.C. ()
N.C. ()
N.C. ()
IO_L08P_2/A23
N9
100E: N.C.
Others: DUAL
IO_L09N_2/A20
IO_L09P_2/A21
M10
N10
100E: N.C.
Others: DUAL
100E: N.C.
Others: DUAL
2
2
2
2
2
2
2
2
2
3
3
IO_L10N_2/VS1/A18
IO_L10P_2/VS2/A19
IO_L11N_2/CCLK
IO_L11P_2/VS0/A17
IP/VREF_2
IO_L10N_2/VS1/A18
IO_L10P_2/VS2/A19
IO_L11N_2/CCLK
IO_L11P_2/VS0/A17
IP/VREF_2
M11
N11
N12
P12
N3
DUAL
DUAL
DUAL
DUAL
VREF
IP_L05N_2/M2/GCLK1
IP_L05P_2/RDWR_B/GCLK0
VCCO_2
IP_L05N_2/M2/GCLK1
IP_L05P_2/RDWR_B/GCLK0
VCCO_2
N6
DUAL/GCLK
DUAL/GCLK
VCCO
M6
M8
P3
VCCO_2
VCCO_2
VCCO
IO
IO
J3
I/O
IP/VREF_3
IO/VREF_3
K3
100E: VREF(INPUT)
Others: VREF(I/O)
3
3
3
3
3
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
N.C. ()
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
B1
B2
C2
C3
D1
I/O
I/O
I/O
I/O
100E: N.C.
Others: I/O
3
IO
IO_L03P_3
D2
F2
F3
G1
F1
H1
G3
H3
H2
L2
I/O
3
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
IO_L05N_3/LHCLK3/IRDY2
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4/TRDY2
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
IO_L05N_3/LHCLK3/IRDY2
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4/TRDY2
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
3
3
3
3
3
3
3
3
3
IO_L08P_3
IO_L08P_3
L1
I/O
3
IO_L09N_3
IO_L09N_3
M1
L3
I/O
3
IO_L09P_3
IO_L09P_3
I/O
3
IP/VREF_3
IP/VREF_3
E2
E1
J2
VREF
VCCO
VCCO
GND
3
VCCO_3
VCCO_3
3
VCCO_3
VCCO_3
GND
GND
GND
GND
N.C. (GND)
GND
A4
A8
C1
C7
GND
GND
GND
N.C. (GND)
GND
GND
GND
GND
GND
DS312 (v4.2) December 14, 2018
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Product Specification
169
XILINX [ XILINX, INC ]
