Spartan-3E FPGA Family: Pinout Descriptions
CP132 Footprint
X-Ref Target - Figure 81
Bank 0
8
1
2
3
4
5
6
7
I/O
9
I/O
L05N_0
GCLK7
10
I/O
L04P_0
GCLK4
11
12
I/O
13
14
I/O
L11P_0
I/O
L01P_0
VCCAUX
PROG_B
GND
GND
TDI
VCCINT L02N_0
TDO
VCCO_0 L07P_0
GCLK10
A
B
C
D
E
F
I/O
I/O
L11N_0
HSWAP
I/O
L10P_0
I/O
I/O
L08P_0
INPUT
L06P_0
GCLK8
I/O
L05P_0
GCLK6
I/O
L02P_0
I/O
L01N_3
I/O
L01P_3
I/O
L09P_0
L03N_0
VREF_0
VCCO_0
TCK
TMS
L07N_0
GCLK11
I/O
L10N_0
I/O
I/O
L04N_0
GCLK5
I/O
I/O
L10N_1
LDC2
I/O
L10P_1
LDC1
INPUT
L06N_0
GCLK9
I/O
I/O
I/O
L09N_0
I/O
L08N_0
L03P_0
GND
GND
GND
L02N_3
L02P_3
L01N_0
VREF_0
I/O
L09N_1
LDC0
I/O
I/O
L03N_3
I/O
L03P_3 VCCINT
L09P_1 VCCINT
HDC
INPUT
GND
VCCO_3
VCCAUX
GND
VCCO_1
VREF_3
I/O
L05P_3
I/O
L04N_3
LHCLK2 LHCLK1 LHCLK0
I/O
L04P_3
I/O
L08N_1
A1
I/O
L08P_1
A2
I/O
A0
I/O
L05N_3
LHCLK3
IRDY2
I/O
L06P_3
LHCLK4
TRDY2
I/O
I/O
INPUT
VREF_1
L07N_1
A3
L07P_1
A4
G
H
J
GND
RHCLK7 RHCLK6
I/O
I/O
I/O
I/O
I/O
L06P_1
L06N_1
A5
L06N_3
L07P_3
L07N_3
A6
GND
I/O
RHCLK4
IRDY1
LHCLK5 LHCLK6 LHCLK7
RHCLK5
I/O
L04N_1
A9
I/O
L05P_1
A8
L05N_1
A7
VCCO_3
I/O
GND
RHCLK3
TRDY1
RHCLK1 RHCLK2
I/O
I/O
I/O
GND
L04P_1
A10
VCCINT
VCCAUX
K
L
VREF_3
VREF_1
RHCLK0
I/O
L03P_1
A12
I/O
L03N_1
A11
I/O
L08P_3
I/O
L08N_3
I/O
L09P_3
VCCINT
I/O
L08N_2
A22
I/O
L09N_2
A20
I/O
I/O
INPUT
I/O
I/O
L01P_2
CSO_B
I/O
L02P_1
A14
I/O
L02N_1
A13
I/O
L03P_2
D7
L04P_2
D4
L05P_2
L10N_2
VS1
GND
M
N
P
GND
VCCO_2
VCCO_1
L09N_3
RDWR_B
GCLK0
GCLK12 GCLK14
A18
I/O
L08P_2
A23
I/O
L09P_2
A21
I/O
I/O
L03N_2
D6
I/O
L04N_2
D3
INPUT
I/O
I/O
I/O
L01N_2
INIT_B
I/O
L11N_2
CCLK
I/O
L01P_1
A16
I/O
L01N_1
A15
I/O
M1
INPUT
VREF_2
L02N_2
MOSI
L05N_2
L07N_2
DIN
L10P_2
VS2
M2
CSI_B
GCLK13 GCLK15
GCLK1
D0
A19
I/O
L02P_2
DOUT
BUSY
I/O
I/O
I/O
I/O
L07P_2
M0
I/O
VREF_2
I/O
L06P_2
D2
L06N_2
D1
L11P_2
VS0
VCCO_2
GND
D5
VCCAUX
GND
GND
VCCINT
DONE
GCLK2
GCLK3
A17
Bank 2
DS312-4_07_030206
Figure 81: CP132 Package Footprint (top view)
I/O: Unrestricted, general-purpose
user I/O
DUAL: Configuration pin, then
possible user I/O
VREF: User I/O or input voltage
reference for bank
16-
22
42-
46
7-8
INPUT: Unrestricted,
CLK: User I/O, input, or global
VCCO: Output voltage supply for
0-2
2
16
4
8
6
4
general-purpose input pin
buffer input
bank
CONFIG: Dedicated configuration
pins
JTAG: Dedicated JTAG port pins
GND: Ground
VCCINT: Internal core supply
voltage (+1.2V)
N.C.: Unconnected balls on the
XC3S100E FPGA ()
VCCAUX: Auxiliary supply voltage
(+2.5V)
9
16
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
173
XILINX [ XILINX, INC ]
