Spartan-3E FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 131 indicates how the 66 available user-I/O pins are
distributed between the four I/O banks on the VQ100
package.
Table 131: User I/Os Per Bank for XC3S100E, XC3S250E, and XC3S500E in the VQ100 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
(2)
I/O
5
INPUT
DUAL
VREF(1)
CLK
Top
0
1
2
3
15
15
19
17
66
0
0
0
1
1
1
0
1
1
1
1
4
8
8
Right
6
Bottom
Left
0
18
2
0(2)
8
5
TOTAL
16
21
24
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Footprint Migration Differences
The production XC3S100E, XC3S250E, and XC3S500E
FPGAs have identical footprints in the VQ100 package.
Designs can migrate between the devices without further
consideration.
DS312 (v4.2) December 14, 2018
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Product Specification
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XILINX [ XILINX, INC ]
