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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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R
Functional Description  
The wide multiplexers can be used by the automatic tools or  
instantiated in a design using a component such as the  
F5MUX. The symbol, signals, and function are described  
below. The description is similar for the F6MUX, F7MUX,  
and F8MUX. Each has versions with a general output, local  
output, or both.  
Table 10: F5MUX Function  
Inputs  
Outputs  
S
0
0
1
1
I0  
1
I1  
X
X
1
O
1
0
1
0
LO  
1
0
0
I0  
I1  
S
0
1
LO  
O
X
X
1
0
0
DS312-2_35_021205  
For more details on using the multiplexers, see XAPP466:  
"Using Dedicated Multiplexers in Spartan-3 FPGAs".  
Figure 18: F5MUX with Local and General Outputs  
Carry and Arithmetic Logic  
Table 9: F5MUX Inputs and Outputs  
The carry chain, together with various dedicated arithmetic  
logic gates, support fast and efficient implementations of  
math operations. The carry logic is automatically used for  
most arithmetic functions in a design. The gates and multi-  
plexers of the carry and arithmetic logic can also be used for  
general-purpose logic, including simple wide Boolean func-  
tions.  
Signal  
Function  
Input selected when S is Low  
Input selected when S is High  
Select input  
I0  
I1  
S
LO  
Local Output that connects to the F5 or FX CLB  
pins, which use local feedback to the FXIN  
inputs to the FiMUX for cascading  
The carry chain enters the slice as CIN and exits as COUT,  
controlled by several multiplexers. The carry chain connects  
directly from one CLB to the CLB above. The carry chain  
can be initialized at any point from the BX (or BY) inputs.  
O
General Output that connects to the  
general-purpose combinatorial or registered  
outputs of the CLB  
The dedicated arithmetic logic includes the exclusive-OR  
gates XORF and XORG (upper and lower portions of the  
slice, respectively) as well as the AND gates GAND and  
FAND (upper and lower portions, respectively). These gates  
work in conjunction with the LUTs to implement efficient  
arithmetic functions, including counters and multipliers, typ-  
ically at two bits per slice. See Figure 19 and Table 11.  
20  
www.xilinx.com  
DS312-2 (v1.1) March 21, 2005  
Advance Product Specification  
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