R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Table 17: IOB Output Switching Characteristics Standard Adjustments
Speed Grade
Description
Symbol
Standard
–6
–5
–4
Units
Output Delay Adjustments
Standard-specific adjustments for output
delays terminating at pads (based on
standard capacitive load, Csl)
TOLVTTL_S2
TOLVTTL_S4
TOLVTTL_S6
TOLVTTL_S8
TOLVTTL_S12
TOLVTTL_S16
TOLVTTL_S24
TOLVTTL_F2
TOLVTTL_F4
TOLVTTL_F6
TOLVTTL_F8
TOLVTTL_F12
TOLVTTL_F16
TOLVTTL_F24
TOLVDS_25
TOLVDS_33
TOLVDSEXT_25
TOLVDSEXT_33
TOLDT_25
LVTTL, Slow, 2 mA
4 mA
9.42
5.77
9.71
5.95
10.68
6.55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 mA
4.11
4.24
4.66
8 mA
2.87
2.96
3.26
12 mA
2.32
2.39
2.63
16 mA
1.70
1.75
1.93
24 mA
1.26
1.30
1.43
LVTTL, Fast, 2 mA
4 mA
6.52
6.72
7.39
2.80
2.88
3.17
6 mA
1.57
1.62
1.78
8 mA
0.46
0.48
0.52
12 mA
0.00
0.00
0.00
16 mA
–0.13
–0.22
–0.31
–0.25
–0.18
–0.17
–0.20
0.67
–0.14
–0.23
–0.32
–0.26
–0.19
–0.18
–0.21
0.69
–0.15
–0.26
–0.36
–0.29
–0.21
–0.19
–0.23
0.76
24 mA
LVDS
LVDS
LVDS
LVDS
LDT
TOBLVDS_25
TOULVDS_25
TOLVPECL_33
TOPCI33_3
BLVDS
ULVDS
–0.20
0.29
–0.21
0.30
–0.23
0.33
LVPECL
PCI, 33 MHz, 3.3 V
PCI, 66 MHz, 3.3 V
PCI–X, 133 MHz, 3.3 V
GTL
1.15
1.19
1.31
TOPCI66_3
–0.01
–0.01
–0.31
–0.17
0.26
–0.01
–0.01
–0.32
–0.18
0.27
–0.01
–0.01
–0.36
–0.20
0.29
TOPCIX
TOGTL
TOGTLP
GTLP
TOHSTL_I
HSTL I
TOHSTL_II
HSTL II
–0.15
–0.17
–0.40
0.03
–0.16
–0.17
–0.41
0.03
–0.17
–0.19
–0.45
0.04
TOHSTL_III
HSTL III
HSTL IV
HSTL I_18
HSTL II_18
HSTL III_18
HSTL IV_18
TOHSTL_IV
TOHSTL_I_18
TOHSTL_II_18
TOHSTL_III_18
TOHSTL_IV_18
–0.17
–0.16
–0.39
–0.18
–0.16
–0.40
–0.20
–0.18
–0.44
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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