R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
I/O standard adjustments are measured using a Tektronix
P6245 TDS500/600 probe (< 1 pf) across approximately 4"
of FR4 microstrip transmission line. The propogation delay
for the 4" of FR4 is characterized separately and subtracted
from the final measurement.
2. Record the relative time to the V or V transition of
OH OL
interest. This is the baseline simulation.
3. Model the actual PCB traces (transmission lines) and
actual loads from the appropriate IBIS models for the
driven devices.
I/O standard adjustment measurements are reflected in the
IBIS model except where the IBIS format precludes it. The
use of IBIS models results in a more accurate prediction of
the propagation delay. The following method may be used to
measure propogation delay:
4. Record the results from the new simulation
5. Compare with the baseline simulation. The increase or
decrease in delay from the baseline simulation should
be added or subtracted to the I/O Output Standard
Adjustment value to predict the actual propogation
delay.
1. Model the output in an IBIS simulation using the
Generalized Test Setup shown in Figure 1.
FPGA
Scope
RT
*
4" 50Ω Microstrip Transmission Line
T
R **
*Terminations are on board and
are configured per the User Guide.
ds083-3_06_072403
Figure 1: Generalized Test Setup
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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