R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
Table 18: Delay Measurement Methodology
(1)
(1)
(2)
Standard
V
V
Meas. Point
V (Typ)
REF
L
H
LVTTL
0
3
1.4
1.65
1.25
0.9
–
–
–
–
–
–
–
–
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
0
0
0
0
3.3
2.5
1.8
1.5
0.75
Per PCI Specification
Per PCI Specification
Per PCI–X Specification
VREF + 0.2
PCI66_3
PCIX33_3
GTL
VREF – 0.2
VREF – 0.2
VREF – 0.5
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
1.2
0.80
1.0
GTLP
VREF + 0.2
HSTL Class I
HSTL Class II
HSTL Class III
HSTL Class IV
SSTL3 I & II
SSTL2 I & II
AGP
VREF + 0.5
0.75
0.75
0.90
0.90
1.5
V
REF – 0.5
VREF + 0.5
VREF – 0.5
VREF – 0.5
VREF + 0.5
VREF + 0.5
VREF – 1.0
VREF + 1.0
VREF – 0.75
VREF – (0.2xVCCO
1.2 – 0.125
1.2 – 0.125
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
0.6 – 0.125
1.6 –0.3
VREF + 0.75
VREF + (0.2xVCCO
1.2 + 0.125
1.2 + 0.125
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
0.6 + 0.125
1.6 + 0.3
1.25
)
)
Per AGP Spec
LVDS_25
LVDS_33
1.2
LVDSEXT_25
LVDSEXT_33
ULVDS_25
LDT_25
1.2
1.2
0.6
0.6
LVPECL
1.6
Notes:
1. Input waveform switches between VLand VH.
2. Measurements are made at VREF (Typ), Maximum, and Minimum. Worst-case values are reported.
DS031-3 (v3.0) August 1, 2003
Product Specification
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1-800-255-7778
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