R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued)
Speed Grade
–5
Description
Symbol
Standard
LVDCI_15
–6
–4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.98
0.00
0.11
0.42
0.98
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.48
0.48
1.00
0.00
0.11
0.43
1.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.49
0.49
1.14
0.00
0.12
0.49
1.14
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.40
0.40
0.56
0.56
T
ILVDCI_15
T
T
T
T
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
GTL_DCI
ILVDCI_DV2_33
ILVDCI_DV2_25
ILVDCI_DV2_18
ILVDCI_DV2_15
T
IGTL_DCI
T
GTLP_DCI
IGTLP_DCI
T
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
LDT_25
IHSTL_I_DCI
IHSTL_II_DCI
IHSTL_III_DCI
IHSTL_IV_DCI
T
T
T
T
IHSTL_I_DCI_18
IHSTL_II_DCI_18
IHSTL_III_DCI_18
IHSTL_IV_DCI_18
T
T
T
T
ISSTL2_I_DCI
ISSTL2_II_DCI
T
T
ISSTL3_I_DCI
T
ISSTL3_II_DCI
T
ILDT_25
T
ULVDS_25
IULVDS_25
Notes:
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18.
DS031-3 (v3.0) August 1, 2003
Product Specification
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