R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
IOB Input Switching Characteristics Standard Adjustments
Table 15: IOB Input Switching Characteristics Standard Adjustments
Speed Grade
–5
Description
Symbol
Standard
–6
–4
Units
Data Input Delay Adjustments
0.00
0.00
0.11
0.42
0.98
0.60
0.60
0.60
0.00
0.00
0.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.35
0.00
0.11
0.42
0.00
0.00
0.11
0.43
1.00
0.60
0.60
0.60
0.00
0.00
0.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.35
0.00
0.11
0.43
0.00
0.00
0.12
0.49
1.15
0.69
0.69
0.69
0.00
0.00
0.00
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.40
0.40
0.40
0.00
0.12
0.49
Standard-specific data input delay
adjustments
T
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVDS_25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ILVTTL
T
T
T
T
ILVCMOS33
ILVCMOS25
ILVCMOS18
ILVCMOS15
T
ILVDS_25
T
LVDS_33
ILVDS_33
T
LVPECL
ILVPECL_33
T
T
PCI, 33 MHz, 3.3 V
PCI, 66 MHz, 3.3 V
PCI–X, 133 MHz, 3.3 V
GTL
IPCI33_3
IPCI66_3
T
IPCIX
T
IGTL
T
GTLP
IGTLP
T
HSTL I
IHSTL_I
IHSTL_II
IHSTL_III
IHSTL_IV
T
HSTL II
T
HSTL III
T
HSTL IV
T
HSTL I_18
HSTL II_18
HSTL III_18
HSTL IV_18
SSTL2 I
IHSTL_I_18
IHSTL_II_18
IHSTL_III_18
IHSTL_IV_18
T
T
T
T
ISSTL2_I
ISSTL2_II
T
SSTL2 II
T
SSTL3 I
ISSTL3_I
ISSTL3_II
T
SSTL3 II
T
AGP
IAGP
T
T
T
LVDCI_33
LVDCI_25
LVDCI_18
ILVDCI_33
ILVDCI_25
ILVDCI_18
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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