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XC2V1000-4FG456C 参数 Datasheet PDF下载

XC2V1000-4FG456C图片预览
型号: XC2V1000-4FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Virtex -II FPGA平台:完整的数据表 [Virtex-II Platform FPGAs: Complete Data Sheet]
分类和应用: 可编程逻辑时钟
文件页数/大小: 311 页 / 1765 K
品牌: XILINX [ XILINX, INC ]
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R
Virtex™-II Platform FPGAs: DC and Switching Characteristics  
IOB Output Switching Characteristics  
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust  
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 14.  
Table 16: IOB Output Switching Characteristics  
Speed Grade  
Description  
Propagation Delays  
Symbol  
6  
5  
4  
Units  
1.43  
1.72  
1.51  
1.83  
1.74  
2.11  
O input to Pad  
T
ns, Max  
ns, Max  
IOOP  
O input to Pad via transparent latch  
3-State Delays  
T
IOOLP  
(1)  
0.51  
1.38  
0.56  
1.45  
0.64  
1.67  
T input to Pad high-impedance  
T
ns, Max  
ns, Max  
IOTHZ  
T input to valid data on Pad  
T
IOTP  
T input to Pad high-impedance via transparent  
latch  
0.80  
0.88  
1.01  
T
ns, Max  
IOTLPHZ  
IOTLPON  
(1)  
1.67  
4.73  
1.77  
5.20  
2.04  
5.98  
T input to valid data on Pad via transparent latch  
T
ns, Max  
ns, Max  
(1)  
GTS to Pad high impedance  
T
GTS  
Sequential Delays  
1.76  
0.95  
1.87  
1.04  
2.15  
1.20  
Clock CLK to Pad  
T
ns, Max  
ns, Max  
ns, Max  
IOCKP  
Clock CLK to Pad high-impedance  
T
IOCKHZ  
IOCKON  
(1)  
(synchronous)  
1.82  
1.94  
2.22  
Clock CLK to valid data on Pad (synchronous)  
Setup and Hold Times Before/After Clock CLK  
O input  
T
0.31/–0.08  
0.19/–0.06  
0.27/–0.05  
0.28/–0.06  
0.19/–0.06  
0.27/–0.05  
0.34/–0.09  
0.21/–0.07  
0.30/–0.06  
0.31/–0.07  
0.21/–0.07  
0.30/–0.06  
0.39/–0.11  
0.24/–0.08  
0.34/–0.07  
0.35/–0.08  
0.24/–0.08  
0.34/–0.07  
T
/T  
ns, Min  
ns, Min  
ns, Min  
ns, Min  
ns, Min  
ns, Min  
IOOCK IOCKO  
OCE input  
T
T
/T  
IOOCECK IOCKOCE  
SR input (OFF)  
/T  
IOSRCKO IOCKOSR  
3State Setup Times, T input  
3State Setup Times, TCE input  
3State Setup Times, SR input (TFF)  
Set/Reset Delays  
T
/T  
IOTCK IOCKT  
T
T
/T  
IOTCECK IOCKTCE  
/T  
IOSRCKT IOCKTSR  
2.41  
1.52  
2.59  
1.67  
2.98  
1.92  
SR input to Pad (asynchronous)  
T
ns, Max  
ns, Max  
IOSRP  
SR input to Pad high-impedance  
T
IOSRHZ  
(1)  
(asynchronous)  
2.39  
5.44  
2.56  
5.98  
2.95  
6.88  
SR input to valid data on Pad (asynchronous)  
GSR to Pad  
T
ns, Max  
ns, Max  
IOSRON  
T
IOGSRQ  
Notes:  
1. The 3-state turn-off delays should not be adjusted.  
DS031-3 (v3.0) August 1, 2003  
Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 3 of 4  
13  
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