R
Virtex™-II Platform FPGAs: Detailed Description
Bitstream Encryption
Partial Reconfiguration
Virtex-II devices have an on-chip decryptor using one or two
sets of three keys for triple-key Data Encryption Standard
(DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.
Partial reconfiguration of Virtex-II devices can be accom-
plished in either Slave SelectMAP mode or Boundary-Scan
mode. Instead of resetting the chip and doing a full configu-
ration, new data is loaded into a specified area of the chip,
while the rest of the chip remains in operation. Data is
loaded on a column basis, with the smallest load unit being
a configuration “frame” of the bitstream (device size depen-
dent).
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the V
pin, when the
BATT
device is not powered. Virtex-II devices can be configured
with the corresponding encrypted bitstream, using any of
the configuration modes described previously.
Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.
A detailed description of how to use bitstream encryption is
provided in the Virtex-II User Guide. Your local FAE can also
provide specific information on this feature.
Revision History
This section records the change history for this module of the data sheet.
Date
Version
1.0
Revision
11/07/00
12/06/00
Early access draft.
Initial release.
1.1
Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II
Switching Characteristics sections.
01/15/01
01/25/01
1.2
1.3
The data sheet was divided into four modules (per the current style standard). A note was
added to Table 1.
•
Under Input/Output Individual Options, the range of values for optional pull-up and
pull-down resistors was changed to 10 - 60 KΩ from 50 - 100 KΩ.
04/02/01
1.5
•
Skipped v1.4 to sync up modules. Reverted to traditional double-column format.
•
•
Added Table 6.
Changed definition of multiply and divide integer ranges under Digital Clock Manager
(DCM).
Made numerous minor edits throughout this module.
07/30/01
10/02/01
1.6
1.7
•
•
Updated descriptions under Digitally Controlled Impedance (DCI), Global Clock
Multiplexer Buffers, Digital Clock Manager (DCM), and Creating a Design.
10/12/01
11/29/01
07/16/02
1.8
1.9
2.0
•
•
•
Made clarifying edits under Digital Clock Manager (DCM).
Changed bitstream lengths for each device in Table 25.
Updated compatible input standards listed in Table 6.
•
•
Changed number of resources available to the XC2V40 device in Table 12.
Clarified Power On Reset information under Configuration Sequence.
09/26/02
12/06/02
2.1
2.1.1
•
Cosmetic edits.
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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