R
Virtex™-II Platform FPGAs: Detailed Description
Table 24: Virtex-II Configuration Mode Pin Settings
(1)
(2)
Configuration Mode
Master Serial
M2
0
M1
0
M0
0
CCLK Direction
Data Width
Serial D
OUT
Out
In
1
1
8
8
1
Yes
Yes
No
No
No
Slave Serial
1
1
1
Master SelectMAP
Slave SelectMAP
Boundary Scan
Notes:
0
1
1
Out
In
1
1
0
1
0
1
N/A
1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin
controls whether or not the pullups are used.
2. Daisy chaining is possible only in modes where Serial DOUT is used. For example, in SelectMAP modes, the first device does NOT
support daisy chaining of downstream devices.
Table 25 lists the total number of bits required to configure
each device.
being cleared. Extending the time that the pin is Low causes
the configuration sequencer to wait. Thus, configuration is
delayed by preventing entry into the phase where data is
loaded.
Table 25: Virtex-II Bitstream Lengths
Device
# of Configuration Bits
360,096
The configuration process can also be initiated by asserting
the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High, and the completion
of the entire process is signaled by the DONE pin going
High. The Global Set/Reset (GSR) signal is pulsed after the
last frame of configuration data is written but before the
start-up sequence. The GSR signal resets all flip-flops on
the device.
XC2V40
XC2V80
635,296
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
1,697,184
2,761,888
4,082,592
The default start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary. One CCLK cycle later, the Global Write Enable (GWE)
signal is released. This permits the internal storage ele-
ments to begin changing state in response to the logic and
the user clock.
5,659,296
7,492,000
10,494,368
15,659,936
21,849,504
29,063,072
The relative timing of these events can be changed via con-
figuration options in software. In addition, the GTS and
GWE events can be made dependent on the DONE pins of
multiple devices all going High, forcing the devices to start
synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as the DCI.
Configuration Sequence
The configuration of Virtex-II devices is a three-phase pro-
cess after Power On Reset or POR. POR occurs when
V
and V
is greater than 1.2V, V
is greater than 2.5V,
CCINT
CCAUX
Readback
(bank 4) is greater than 1.5V. Once the POR volt-
CCO
In this mode, configuration data from the Virtex-II FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary Scan mode.
ages have been reached, the three-phase process begins.
First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
the Virtex-II Platform FPGA User Guide.
Configuration is automatically initiated on power-up unless
it is delayed by the user. The INIT_B pin can be held Low
using an open-drain driver. An open-drain is required since
INIT_B is a bidirectional open-drain pin that is held Low by a
Virtex-II FPGA device while the configuration memory is
DS031-2 (v3.0) August 1, 2003
Product Specification
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