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Virtex™-II Platform FPGAs: Detailed Description
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One dedicated SOP chain per slice row (two per CLB
row) propagate ORCY output logic signals horizontally
to the adjacent slice. (See Sum of Products.)
Design Entry
All Xilinx ISE development systems support the mainstream
EDA design entry capabilities, ranging from schematic
design to advanced HDL design methodologies. Given the
high densities of the Virtex-II family, designs are created
most efficiently using HDLs. To further improve their time to
market, many Xilinx customers employ incremental, modu-
lar, and Intellectual Property (IP) design techniques. When
properly used, these techniques further accelerate the logic
design process.
One dedicated shift-chain per CLB connects the output
of LUTs in shift-register mode to the input of the next
LUT in shift-register mode (vertically) inside the CLB.
(See Shift Registers, page 16.)
Creating a Design
Creating Virtex-II designs is easy with Xilinx Integrated Syn-
thesis Environment (ISE) development systems, which sup-
port advanced design capabilities, including ProActive
Timing Closure, integrated logic analysis, and the fastest
place and route runtimes in the industry. ISE solutions
enable designers to get the performance they need, quickly
and easily.
To enable designers to leverage existing investments in
EDA tools, and to ensure high performance design flows,
Xilinx jointly develops tools with leading EDA vendors,
including:
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Aldec
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Cadence
As a result of the ongoing cooperative development efforts
between Xilinx and EDA Alliance partners, designers can
take advantage of the benefits provided by EDA technolo-
gies in the programmable logic design process. Xilinx devel-
opment systems are available in a number of easy to use
configurations, collectively known as the ISE Series.
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Exemplar
Mentor Graphics
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Model Technology
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Synopsys
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Synplicity
ISE Alliance
Complete information on Alliance Series partners and their
associated design flows is available at www.xilinx.com on
the Xilinx Alliance Series web page.
The ISE Alliance solution is designed to plug and play within
an existing design environment. Built using industry standard
data formats and netlists, these stable, flexible products
enable Alliance EDA partners to deliver their best design
automation capabilities to Xilinx customers, along with the
time to market benefits of ProActive Timing Closure.
The ISE Foundation product offers schematic entry and
HDL design capabilities as part of an integrated design
solution - enabling one-stop shopping. These capabilities
are powerful, easy to use, and they support the full portfolio
of Xilinx programmable logic devices. HDL design capabil-
ities include a color-coded HDL editor with integrated lan-
guage templates, state diagram entry, and Core generation
capabilities.
ISE Foundation
The ISE Foundation solution delivers the benefits of true
HDL-based design in a seamlessly integrated design envi-
ronment. An intuitive project navigator, as well as powerful
HDL design and two HDL synthesis tools, ensure that
high-quality results are achieved quickly and easily. The ISE
Foundation product includes:
Synthesis
The ISE Alliance product is engineered to support
advanced design flows with the industry's best synthesis
tools. Advanced design methodologies include:
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State Diagram entry using Xilinx StateCAD
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Physical Synthesis
Incremental synthesis
RTL floorplanning
Automatic HDL Testbench generation using Xilinx
HDLBencher
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HDL Simulation using ModelSim XE
Direct physical mapping
Design Flow
Virtex-II design flow proceeds as follows:
The ISE Foundation product seamlessly integrates synthesis
capabilities purchased directly from Exemplar, Synopsys, and
Synplicity. In addition, it includes the capabilities of Xilinx
Synthesis Technology.
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Design Entry
Synthesis
A benefit of having two seamlessly integrated synthesis
engines within an ISE design flow is the ability to apply alter-
native sets of optimization techniques on designs, helping to
ensure that designers can meet even the toughest timing
requirements.
Implementation
Verification
Most programmable logic designers iterate through these
steps several times in the process of completing a design.
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
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