R
Virtex™-II Platform FPGAs: Detailed Description
Revision
Date
Version
•
•
Added qualification note to Figure 13, page 11.
Corrected sentence in section Input/Output Individual Options, page 4, to read “The
optional weak-keeper circuit is connected to each user I/O pad.”
05/07/03
2.1.2
•
Corrected typographical errors in Table 3 for names of HSTL_[x]_DCI_18 standards.
•
•
Removed Compatible Output Standards and Compatible Input Standards tables.
Added new Table 5, Summary of Voltage Supply Requirements for All Input and
Output Standards. This table replaces deleted I/O standards tables.
Added section Rules for Combining I/O Standards in the Same Bank, page 6.
06/19/03
08/01/03
2.2
3.0
•
All Virtex-II devices and speed grades now Production. See Table 13, Module 3.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
•
Virtex™-II Platform FPGAs: Introduction and Overview
(Module 1)
•
•
Virtex™-II Platform FPGAs: DC and Switching
Characteristics (Module 3)
•
Virtex™-II Platform FPGAs: Detailed Description
(Module 2)
Virtex™-II Platform FPGAs: Pinout Information
(Module 4)
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
40
XILINX [ XILINX, INC ]
