R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Period Tolerance: the allowed input clock period change in nanoseconds.
1
T
=
CLKIN
F
+ T
_
IPTOL
T
CLKIN
CLKIN
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
Phase Offset and Maximum Phase Difference
Ideal Period
Actual Period
+/- Jitter
+ Maximum
Phase Difference
+ Phase Offset
DS001_52_090800
Figure 22: Period Tolerance and Clock Jitter
44
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DS077-3 (v2.3) June 18, 2008
Product Specification